These range from low-level solutions to advanced tools that incorporate finite element modeling/analysis and layout support. Most of these tools have evolved from the IC world, where rectangles make up typical geometries. Although there have been recent innovations in the development of MEMS layout tools, MEMS layout designers still face some common issues and roadblocks while attempting to create lithographic masks that correspond with the original device design, specifically in the areas of drawing, design rule checking (DRC) and output.

MEMS versus IC requirements

In many cases, the mechanical/optical/fluidic nature of MEMS structures involves arbitrary geometries composed of arcs, curves, circles and other multi-polygonic shapes. Unfortunately, such geometries have not traditionally been the focus of IC layout tools. For example, if the software supports full curves and multi-polygons, the layout designer must still have a thorough understanding of how the data is fractured by the mask house to ensure that the electronic file resolution is replicated on the physical quartz mask. In addition, understanding the three-dimensionality of the topography is required. This is because unlike most VLSI (very large-scale integration) processes, MEMS processes have a much wider range in the thickness of the thin film (about 10 micrometers versus one micrometer). A host of features differentiate MEMS layout tools from those of the IC field, due to the free-form nature of MEMS structures. First, the ability to draw curves or all-angle polygons (i.e. commands that enable arcs, circles, tori and bezier curves) is a departure from the rectangle-focused IC tools. This is useful for applications such as microfluidic channels and mechanical reliefs. Most IC-based layout tools do not support the precision drawing of curves (i.e. for micro-turbines) and often times the user must create additional macros in order to define accurately the flow channel point by point via a coordinate data file. Second, the ability to snap, measure and accurately edit these free-form polygonic shapes becomes tedious because most layout tools are grid-based.Another main difference between IC geometries and MEMS geometries is the magnitude of range in size. While typical transistor blocks may cover 20x20 micrometers areas, MEMS geometries may have 5 micrometers features, and an overall dimension of 1mm. This wide range in size can result in constant zooming in and out during the design process. Thus, some MEMS designs require the ability to snap to corners, midpoioints or user specified relative distances without zooming in.

Drawing

When drawing any geometry for IC fabrication, the designer is essentially designating an area which is either clear or dark (field). This can be complex when the designer uses a mechanical CAD tool. In mechanical drawings (e.g. DXF format), 'zero width' lines are utilized, however mask fabrication houses do not recognize these types of lines. To account for this ambiguity, all features drawn for mask fabrication must be in the shape of enclosed polygons. However, if the polygon is irregular in shape, (i.e. a square with a hole in the center) the object must be drawn in a specific manner, with only one enclosing boundary, so the mask manufacturer knows which areas are clear or dark. For MEMS designers, this rule can become cumbersome, for example, when designing a free-standing plate with thousands of release holes. As a solution, two-way conversion utilities between DXF and GDSII file formats (and many more) are available as separate programs and can also be built into some layout tools.Consequently, Boolean drawing operations and derived layers become indispensable in situations where many layers require curved geometries. Boolean drawing operations enable the designer to use logical and other operations (e.g. AND, OR, NOT, XOR, GROW, SHRINK, Subtract) to create new shapes from arbitrary polygons. These operations can be used to create entirely new layers (derived layers) from existing ones. For example, a mask for a flow channel may require a 10micron border of metal all around it. Using the Boolean algorithm, the designer would only require one command to grow and subtract from the original layer. Any subsequent change in the original flow channel would automatically be generated in the new derived layer.

Design rule checking

As MEMS processes become more standardized and devices gain complexity, DRC can be used to find errors before tape-out. While DRC tools have always existed for IC designers, they typically are not used in MEMS. The free-form nature of the MEMS processes results in varying design rules depending on the MEMS fab and associated tooling, and many DRC tools are not able to perform operations on all-angle polygon geometries. The implementation of custom design rules is awkward.Following are some examples of potential design rules for a five-layer electromagnetic actuator process:There must always be Insulation 1 underneath the Permalloy layer when it is over(lapping) Copper 1.There must always be Insulation 2 above the Permalloy layer when Permalloy is overlapping Copper 2.Copper 1 wires must have more than 4µm of spacing between them.Copper 2 wires must have more than 4µm of spacing between them.The DRIE mask should never have any other layer overlapping it. (4µm separation).Many of these rules can now be implemented relatively quickly on a custom basis in newer versions of layout software.

Output issues

The most common mask fabrication format is GDSII, which imposes finite limitations on the discretisation of the curved geometries. Although the MEMS designer may have drawn 0.25µm resolution circles, the GDSII vertex limit coupled with the limits of the fracturing software at the mask maker may decrease the resolution by 5x. In the past, the GDSII standard has imposed an artificial limit of 200 vertices per polygon. Most fracturing software today has the ability to accept over 2048.One example of this is a 1000µm diameter circle which is 'polygonized' by the GDSII conversion. With the 200 vertex limit, the circle is fabricated as a 200-sided polygon with each edge approximately 15µm. With the 2048 sides, the circle is rendered more precisely (1.5µm edge length). However, with larger and larger circles (or complex curved structures), the geometries must be segmented into smaller polygons so that the edge resolution can be maintained. Until now, this type of segmenting had to be completed by the layout designer who would compensate for the limitations of the mask fracturing software. Now, this process can be done automatically by MEMS savvy layout algorithms.Certain MEMS structures can be output sufficiently with a high-resolution film (transparency) from a Linotronic 3386 (dpi) printer available at professional print and color separation firms for about $20 per film. With about a 10-15µm pixel size, these films are well suited for quick masks and larger size MEMS structures. The only requirement is EPS output from the layout software. In fact, many academic fabs with a 10x stepper are able to make 2µm features at a very low cost with this technique. However, if not properly handled, the stretching of the film can change the layer-to-layer registration for tight lithography. Furthermore, the minimum line widths and spacing achievable is different for horizontal and vertical features.

Conclusion

MEMS mask designers must have a clear understanding of the full mask fabrication process flow to ensure accurate rendering of curved geometries on the reticle. Today, more and more IC layout tool firms are bridging the gap between the needs of MEMS designers and the needs of IC designers. Without question, functionality such as DXF input/output, better curve/arc drawing tools, full DRC and Boolean operations are essential features for MEMS designers. Robust implementation of the MEMS features in IC tools will be a benefit to the industry by reducing costs and shortening the development time.