The most common technique involves the use of a Digital Down-Converter (DDC). The DDC process is often carried out using custom ASIC chips, of which there are many different varieties available, although DDC FPGA cores are also available from many vendors. Typical DDC functionality is illustrated in figure 1. Functions include a frequency shift of -f to centre the required channel at DC, including conversion from real to complex. Filtering removes all the unwanted out-of-band signal components that would otherwise alias into the passband on decimation; and decimation by a user-specified factor D. A further decimate-by-4 lowpass filter corrects for the CIC filter shape and apply a user-defined filter to the output. Usually, in a digital receiver where the DDC output is being fed into a demodulator, the required output rate is several times the symbol rate.Most DDCs permit the user to control the decimation rate and the filter characteristics, although the precise level of flexibility depends upon the implementation. Typically, a fully programmable DDC ASIC chip supports around four independent channels, extracted from digitised inputs, although some reduced functionality DDC chips are now available that support larger numbers of channels. DDC cores for FPGA often have more flexibility, though they can require a lot of silicon.

Wideband down converter solutions

There are many cases where several hundred relatively narrowband (100s of kHz) channels are required to be down-converted from a single wideband (100s of MHz) digitised data stream. In this case, it is normally attractive to replace a large number of ASIC DDC chips with a single integrated channeliser. If the required signal parameters are known at design time, it is possible to eliminate some of the flexibility of the DDC approach to provide far more silicon-efficient down-converter structures that are tailored to meet specific requirements. Generally, these structures are implemented in FPGA since they are not required for volume applications; however, there is no limitation to their implementation on ASIC. A further advantage of using FPGA technology is that it provides a degree of future-proofing, in that if a different channel structure is required at a later date, a different FPGA image may be provided that meets this requirement without the need for a complete redesign of the board. RF Engines has various patented and proprietary channeliser architectures that meet a wide range of requirements. Wideband DDC cores provide down-conversion of a few relatively wideband sources from a wideband input source. Flexible multi-channel down-converter cores provide channelisation of a large number (a few hundred) of relatively narrowband sources from a wideband input. These channeliser cores can be used to efficiently extract signals from any dynamically selectable frequency with a very wide variety of channel sample rates and filter characteristics. Then there are the fixed multi-channel down-converter cores that channelise a very large number (more than a thousand) of channels from fixed channel locations, where the channels have a fixed spacing and all share the same filter shape and output sample rate. Figure 2 summarises the applications for the different down-converter techniques. Wideband DDC cores are seen to provide significant flexibility for a limited number o of channels; the fixed down-converter cores are at the other end of the scale, providing limited flexibility but a large channel capacity. In general, silicon usage increases both with the number of channels and the required flexibility. The remainder of this article concentrates on one of the techniques used by RFEL to provide fixed multichannel down-converters: The "WOLA (Weight-Overlap-Add) FFT" or "Polyphase FFT". In particular we concentrate on the requirement to use Mixed Radix FFTs.

The WOLA or Polyphase FFT

It is well known that a K-point FFT may be considered as a critically decimating filterbank, providing K equally spaced channels, all filtered by a K-point moving average filter response and decimated by a factor D=K. For the WOLA FFT, an additional filtering stage is placed prior to the FFT to modify the filter response and to change the decimation factor. The Polyphase FFT technique is similar but permits less flexibility in the selection of the decimation factor. In general, this article refers to the WOLA FFT, though the appropriate implementation should be chosen for each case. The four design parameters for the WOLA FFT are:The input sample rate, fs;The length (number of points) of the FFT, K, which provides the channel spacing from the equation, fdelta=fs/K;The decimation factor through the WOLA, D, which provides the output sample rate per channel via the relation, fdemod=fs/D.The filter impulse response, {h[n], 0 n<L-1}.The channel spacing, fdelta, is fixed by the communication standard and the required sample rate fdemod is specified for the demodulator; fdemod is normally an integer times the symbol rate. It is easily shown that for a filterbank to meet the above requirement, integer values of K and D must be found that satisfy: K/D= fdemod/fdeltaOne structure for implementing the WOLA DFT is as shown in figure 3, where all lines represent complex data. The input is divided into frames of D samples and passed into a delay line. This is then weighted by the filter impulse response, divided into blocks of K samples and overlapped to pass through the FFT. A final step is required to correct the phase of the outputs.

Mixed radix FFT designs

The channel spacing, fdelta, and demodulator rate, fdemod, are generally chosen to meet other requirements, resulting in values for K and D that are not powers of 2. For instance, GSM has a channel spacing of 200kHz and a symbol rate of 1625/6=270.833kHz. From these numbers and the above equations, a demodulator that requires two samples per symbol provides D=48n and K=65n, where n is an integer chosen to meet additional requirements such as sample rate, number of channels or usable input bandwidth. For instance, if the requirement was to provide 200 channel outputs, n=4 could be chosen, yielding the solution shown in figure 4.The ADC output is first applied to a DHBF (Distributed Halfband Filter), which converts the real input signal to a complex output at half the rate. Frequency offset correction is then applied to compensate for a systematic frequency offset across all channels, due to Doppler shift or frequency error. The signal is then passed into the WOLA-FFT, which provides 260 outputs with the required spacing and rate. It is assumed that only the 200 central outputs are required; the remainder are in the analogue anti-aliasing filter transition bands and are discarded. Alternative values of n could be chosen that would provide different number of channels and FFT length, however, the important thing is that the FFT is always going to have K = 65n points. This means that it must be a mixed radix solution with radices of 13, 5 and factors of n. There is no solution of this type that will provide the required channel spacing and output sample rate without carrying out a DFT of this length, which implies a mixed radix FFT implementation. RF Engines has generated a design for the above 200 channel GSM channeliser and have shown that for a 14-bit ADC, it will fit on a Xilinx Virtex-II 6000 FPGA. In another recent design that required more than 1500 channels to be precisely extracted from a spectrum bandwidth in excess of 40MHz, 2-point, 3-point and 13-point DFDFT cores were integrated to produce a 1872-point FFT. Again, a radix-2 FFT would not have been able to meet the channel spacing and sample rate requirements for this application. The design fitted comfortably within a Xilinx Virtex Pro50 FPGA. By eliminating the unneeded functionality, channelisation architectures can be derived that provide a much larger number of channels with the same amount of silicon. It is worth noting that for all the channelisers described here, an inverse architecture is available to meet the multi-channel up-conversion requirement.