The HardCopy II family offers a unique FPGA front-end design methodology and costs as little as $15 for 1 million ASIC gates. Built on a fine-grained architecture, the structured ASICs deliver a level of gate densities, performance, and low power consumption that make them a good alternative to a broad range of ASIC and ASSP implementations. HardCopy II devices deliver up to 2.2 million ASIC gates, 8.8 million bits of RAM, and over 350 MHz system performance. The devices enable seamless migration from a pin-compatible, functionally equivalent Stratix II FPGA prototype, minimising development risk and development costs. Using the Quartus II design software and the Stratix II FPGA family, designers can fully validate their design in system and at speed. The Quartus II software automatically generates the files to hand off to Altera's HardCopy Design Center which performs a turnkey migration of the design to a HardCopy II-structured ASIC and delivers fully tested prototypes within 8 to 10 weeks. Designers have the option of using their existing synthesis, verification, timing analysis, and logic equivalency checking tools from Cadence, Mentor Graphics, Synopsys, and Synplicity. HardCopy II devices deliver over 50% core power reduction from the design implemented in the Stratix II FPGA. Its interface circuitry supports external memory at 233 MHz for SDRAM and 250 MHz for RLDRAM II. Additionally, they support 1 Gbps differential I/O and high-speed interfaces, including 10 Gb Ethernet, SFI-4, SPI-4.2, HyperTransport, RapidIO, and UTOPIA Level 4 interfaces up to 1 Gbps.
