Designed as sub-20ns access time, radiation hardened 4-Mbit SRAMs, the AT60142F and AT60142FT CMOS asynchronous devices are organised as 512K x 8-bits. Both devices combine rad-hard capabilities, a latch-up threshold and a total dose up to 70MeV and 300Krad respectively, with a fast access time over the full military temperature range. The AT60142F achieves 15ns (66MHz) access times at a 180mA operating current, while the 5V-tolerant variant, AT60142FT, achieves 17ns at 170mA. Additional operating current specifications are available at various speeds ranging from 1 to 40MHz in either read or write modes. Compared to the other 5V 4Mbit SRAMs, the AT60142FT achieves a 53% savings in power consumption at the same speed. This has been achieved by replacing the implicated buffers by their 5V tolerant version, resulting in a guaranteed operating speed of 17ns or 59MHz. Both the AT60142F and AT60142FT operate with a 3.3V bias while an internal regulator biases the memory cell at 2.5V. The characterised SEU-induced error rate is as low as 1E-7 error per bit per day. Both chips are housed in a 36-pin 500-mil wide dual-in-line flat pack.
