Components containing adaptive circuits offer much in the way of potential advantages to the systems utilising them. A historically popular example for commercial communication systems is the use of predistorted power amplifiers (PPAs), whether by digital or other means, whereby a PA of more moderate capability is able to outperform those with greater linearity. Today's adaptive circuits are even more challenging because of the technologies involved. The higher frequencies require that circuit design itself consider distributed effects, so much so that designs might best be layout-driven rather then designed in a traditional "top-down," schematic-based flow. Complex modulated waveforms, while not obsolescing multi-tone, frequency-based design, do not clearly correlate to linear and nonlinear frequency-based simulations; they require other techniques, such as shooting methods or envelope simulation. Finally, the adaptive component is more often than not a software-based design. This adds yet another design domain, which, if not included early in the design process, can cause design iterations due to "bugs." Optimising overall circuit performance can be difficult or impossible when the interactions among all of these design areas cannot be considered simultaneously.In this article, a simple example (Figure 1) of real-time concurrent design across these disparate design domains is shown. By way of a basic high-frequency amplifier, digitally-controlled attenuator, power sensor, and adaptive control algorithm, the example begins with a simple attenuator, sensor, and algorithm design that incrementally and concurrently improves the design. The need to create a more capable attenuator of frequency and power in order to couple to both the amplifier and the algorithm is demonstrated. The example also illustrates the fact that this design challenge is best-handled when considered concurrently, rather than serially.
Serial design flow
A serial design flow is shown in Figure 2. The design proceeds in a top-down manner where the design is partitioned based on parametric budgeting into smaller and smaller pieces until the individual design components, specified by the budgeted parametric definitions, are realised and only then integrated. At this point, the second, debugging, phase proceeds to identify interactions among the design domains. At the same time, parts are redesigned for new parametric performance with the understanding that such performance minimises or moves the interactions to a state where system performance is acceptable. The typical serial design flow is a consequence of the difficulties in moving data accurately and quickly among domains. Inherent in each step in the flow is a software EDA or CAD tool with its own database capturing the portion of the design represented by that step, with the assumption that the whole database of the design is represented by the sum of the parts. This impedes or totally inhibits concurrency because at the heart of concurrency is the notion of interaction among disparate design domains.
Concurrent design flow
A concurrent design flow is shown in Figure 3. In concurrent design, the intention is to bring the debugging phase up into the earlier top-down phase, and with it, the software subflow. The debugging phase is enabled by considering software simulations, or so-called "virtual prototypes" of the individual hardware blocks and their integration. This provides at least the possibility, during the design phase, for the removal or mitigation of design problems normally uncovered only during the debugging phase. The enabling feature of the concurrent flow is a unified data model, versus the distributed data model in the serial flow depicted in Figure 2.The challenge for high-performance product design teams today is that design phases are traditionally isolated by separate EDA design and analysis environments, incompatible databases and use tools, and models that are not designed for the gigahertz frequencies at which next-generation electronics products are operating. The separate EDA environments and databases prevent designers from analysing and optimising circuit performance early in the design cycle, where it is most critical.A new, highly integrated co-chip/package/module EDA solution is needed that is developed specifically to address the complex cross-domain issues inherent in the design of next-generation high-performance/high-frequency products. The software must be designed around a single, object-oriented database that is inherently synchronised with schematic, simulation, and layout data, enabling easy integration of all the design phases within one environment. The core technology must be a unified data model that is open and flexible and that enables interactive tradeoffs between system requirements and circuit implementation throughout the design cycle, allowing engineers to get their designs right the first time and shortening time-to-market.
