Consumer products increasingly need to serve a variety of functions - multitasking as a still camera, mobile telephone, MP3 player, camcorder, etc. Therefore, telecommunications equipment has to anticipate the changing standards that continue to litter its path. Automotive systems must keep up with changes in telematics and infotainment demands. Industry-wide there is a shift away from the inflexibility of RISC-based designs, or conversely the relatively low speed of discrete DSP processors, towards a more versatile option. As a result, a number of innovative firms are looking at ways to circumvent these incumbent problems.

The RISC factor

Different incarnations of Tensilica's Xtensa processor have been doing the rounds for several years now. The most recent version, the LX, has further increased performance with greater I/O bandwidth and compute parallelism. It has up to 64 general-purpose physical registers, 6 special purpose registers and 80 base instructions, with a compact RISC instruction set (of 16 or 24, rather than 32bits). It aims to enable designers to achieve significant code size reductions compared to conventional RISC-based cores. This helps raise the performance and slash the power dissipation - the two most vital requirements of current SoC design. Both BDTI and EEMBC benchmarks show that they outpace ARM or MIPS cores by a wide margin.Californian start-up Stretch has taken the Tensilica product offering one stage further with the S5620 software-configurable processor. The chip integrates a 300MHz, 32bit Xtensa core with built-in programmable logic, interface to IBM PowerPC processors, embedded memory, and a comprehensive set of peripherals. It delivers a complete off-the-shelf processing solution, for those who do not want to have to go to the trouble of embedding the IP they have obtained onto silicon.

Mega-Brits

The UK is rapidly establishing itself as the home of reconfigurable processor technology, with several of the leading exponents to be found on English soil. Earlier this year, ARC International released the ARC 600 and 700 configurable cores to deliver pre-optimised size, speed and power characteristics. These cores help developers deal with the increasingly complex demands of system designs in areas such as data storage, and network processing. Each core eats up significantly less silicon area and power than fixed processors solutions. The ARC 600 cores use an efficient five-stage pipeline to deliver 1.3DMIPS/MHz of performance, while its sibling draws upon a seven-stage pipeline to deliver 1.2DMIPS/MHz. Each core has DSP capability as a standard feature with optional signal processing functions in the form of the XY Advanced DSP subsystem. Bristol-based Elixent has just unveiled its latest Reconfigurable Algorithm Processing (RAP) architecture. The D-Fabrix Version 2.0 allows designers to implement signal processing algorithms in approximately half the silicon area required by previous systems, while also reducing power consumption. The offering is designed to focus on the particular needs of the mobile multimedia and communications applications. The architecture makes use of enhanced routing and switching to increase performance density. Processor resources can be time-shared so that each function can be executed sequentially. Instead of all the hardware being needed, a smaller RAP device can be used to meet the performance requirements.Just a few miles down the road, amongst the Georgian sandstone buildings of Bath, you will find picoChip. The company's picoArray is a highly parallel, Multiple Instruction Multiple Data (MIMD) architecture which is composed of processing elements of various types linked together by the patented picoBus interconnect. There are two types of processing element: 16bit Harvard architecture processors each with 3-way LIW, and lococal memory/hardware co-processors to accelerate specific functions. The picoBus which links the processing elements provides acres of bandwidth and efficiently operates totally deterministic communications between each element. Data flow paths group the processors into chains or arrays, allowing the bus to operate routinely at >90% maximum capacity. The performance of a single PC102, the latest generation of picoArray, is equivalent to 340 ARM processors. It delivers 4OGMACs and runs at a rate of 3300Gigabits/sec, which is 10 times faster than current ADI Blackfin devices and five times faster than the latest StarCore architecture. The arrays lend themselves particularly well to wireless, and are currently getting a lot of design-in action in both 3G and WiMAX infrastructure. The fact that both technologies are seeing more than their fair share of flitting between standards only helps to underline the importance of a reconfigurable solution.It looks likely to be a more flexible future, but the established chip manufacturers are not going to hand over their business on a plate to these «Johnny-come-latelys". Whether they will choose to try to develop their own product offering, or take the easier route and license the cores, they are certain to have a hand in what transpires. The survival of the reconfigurable processor vendors may be as dependent on their negotiating skills as it is on their design expertise.