PDs offer end users great benefits by going into locations without AC outlets and drawing power from centrally located uninterruptible power supplies (UPS). PDs need an 802.3afcompliant Power-over-Ethernet interface and a DC/DC converter. Products such as the LTC4267 PoE-powered device controller can simplify implementation of both of these, reducing design time and aiding in 802.3af compliance. However, ICs cannot tackle all of the challenges of PoE: some issues must be resolved at the board and system levels. Furthermore, the same solution does not suit everyone; designers need freedom to tailor solutions to their application while ensuring interoperability. Most of the IEEE 802.3af standard for PDs can be described by the PD's I-V curve as shown in Figure 1. The curve is broken up into three voltage ranges: detection from 2.7 to 10.1V, classification from 14.5 to 20.5V, and power from 30 to 57V. The behavior of the PD within these ranges is mandated by the IEEE standard, but the transitions between ranges are equally important for interoperability. The PSE probes the detection region to distinguish the PD with a 25kOhm resistance from non-powered devices with 150Ohm common-mode termination. In the classification range, the PD's current corresponds to the amount of power it needs to operate. When its input or port voltage exceeds 30V, the PD begins drawing power from the cable to operate the rest of its circuitry. In most PDs the 48V input from the Ethernet port is converted to 3.3 or 2.5V for the PD's circuitry. The schematics of Figures 2 and 3 show a circuit that handles the PD's entire PoE interface, which includes DC/DC conversion. With this grouping, the PoE interface becomes a self-contained power supply, allowing PD designers to concentrate on the circuitry and software that differentiates their PD from others.
Connecting to the cable
Both the PD's PoE interface and Ethernet PHY must connect to the RJ-45 jack (Figure 2). The 75Ohm common-mode-termination resistors are AC-coupled so they do not interfere with PoE. The termination is connected on the cable side of the common-mode choke so the choke's inductance and hence high AC impedance do not affect the impedance of the termination. Wiring and circuit board traces in these paths need special attention for their resistance to be kept down. On the circuit board, use wide traces and place components close together to reduce trace length. In the magnetic components (T1-T6), controlling wire resistance is particularly important to ensure DC current does not saturate T5 or T6 and block data transfer. Autotransformers T1 and T2 must be wound so the center tap sees the same resistance to both wires of the pair. Even when T1 and T2 are wound perfectly, cable resistance may still cause some DC differential voltage. The magnetic components can encourage the resulting DC current to flow through T1 or T2 by making them lower resistance than chokes T3, T4 and the data transformers T5, T6. Figure 2 illustrates this, with wider lines representing low resistance wires. Connecting the PD to the spare pairs is much simpler because these wires do not transfer data (as shown in Figure 2); there is no need for magnetic components. (For Gigabit Ethernet, which does put data on the spare pairs, connect them with the same magnetic components as the data pairs in Figure 2.) Once those components have extracted the power and data from the cable, the PD looks the same whether viewed from the spare or the data pairs. In fact, the requirements on the PD's I-V curve are the same for both voltage polarities and both pairs. The pair of diode bridges - D1 andD8 in Figure 3 - combines signals from both pairs into a unipolar output, allowing one 802.3af-compliant PD interface (controlled by the LTC4267 in Figure 3) to service both inputs pairs and both polarities. Beyond the diodede bridges, Figure 2 has a transient voltage suppressor (TVS) to protect the PD's input because ringing, overshoot transients, static electricity, ground differences, and so on can put hundreds or thousands of volts on the cable. Because the cable has up to 0.05µF with low series inductance and resistance, the energy behind these voltages can be quite large. Transient voltage suppressors can absorb much of this energy, but the rest of the PoE interface must be designed to survive an additional 20 to 30V above the operating range until the TVS limits the voltage.
Detection
Detection is the first and most important step in establishing a PoE connection. A PD has 25kOhm of common-mode resistance while most non-powered devices feature 150Ohm or open-circuit common-mode termination. Between 2.7 and 10.1V, the PD must have a detection signature resistance of 25±1.25kOhm. Besides the resistor itself, which is included with the LTC4267 in Figure 3, the diode bridges are the most important elements of the PD's 25kOhm detection signature. The forward voltage of the diodes adds offset to the signature, which the standard requires to be less than 1.9V (sufficient for silicon diodes at -40°C). Non-linear series resistance of the diodes affects the signature as shown in Figure 4. Reverse-biased bridge diodes add leakage so two diodes in parallel must leak less than the IEEE's 10µA limit with 10.1V of reverse bias. The LTC4267 solves many of these problems by integrating and optimising the signature resistance, shown in Figure 4, to compensate for the diode bridges and its own supply current, removing this burden from the designer.
Classification
Following a successful detection, most PSEs will classify the PD to determine how much power it will consume. Classification improves a PSE's power management, allowing it to power more PDs from the same wattage power supply. For example, nine PDs that consume 5W but advertise themselves as class 3 maximise the capabilities of a 150W supply since the PSE must allocate 15.4W to each class 3 PD. If the same PDs uses class 2, the PSE allocates 7W to them and its 150W can supply 21 PDs. Use Table 1 to select the appropriate class for your PD by choosing the lowest class number (1, 2, or 3) whose maximum continuous power and peak current is less than that of the PD. Classification is accomplished by the PSE, forcing the port voltage into the classification range and then measuring the PD's current. Throughout the classification region, the PD's current must be within one of the three ranges listed in Table 1. Although the 802.af standard puts more than 5V between detection and classification, most of this range is consumed by the variation of diode forward voltage (VF) with temperature. At high temperatures, the diode's VF will be about 0.5V while at low temperatures it is about a 0.9V so the LTC4267 must switch from detection to classification within just over 3V. Within this range, the device does its best to maximise interoperability by slowly turning on the classification current; note the slope of the typical I-V curve in Figure 1. If the transition between detection and classification is not handled smoothly, oscillations can occur because the PD's classification current may cause the port voltage to drop out of the classification range. Even with a stable voltage from the PSE, rapid changes in the PD's current combined with inductance of 100m of cable can cause ringing. Negative resistance from turning off classification current above 20.5V can cause more severe oscillations and interoperability problems. For maximum interoperability, PDs should attempt to have smsmooth, monotonic I-V curves like that shown in Figure 1.
Powering on
When the PD turns on and begins drawing its power from the cable, the PD design becomes more complicated because the PoE interface, DC/DC converters and the rest of the PD's circuitry must work together to maintain 802.3af compliance. The LTC4267 includes the two most important members of this cooperative, the PoE interface and the DC/DC converter. The device waits until its input reaches 36V before beginning to draw power and limits inrush current to 140mA (Figure 1). By waiting until 36V, it puts 6V of hysteresis between its turn-on (36V) and turn-off (30V) voltages. This hysteresis prevents the PD from oscillating on and off if the port voltage drops due to the LTC4267's increased current draw. Once the PD is powered up, the device switches to a 375mA current limit, allowing the PD get the full 12.95W from the cable. PDs with a higher inrush-current limit will need a larger hysteresis; 802.3af allows up to 12V, to prevent oscillations. PDs are not required to implement a current limit of their own provided they can power up within 50ms with the 400mA to 450mA current limit of the PSE. PDs that do not limit current themselves or power up in 50ms will have their power turned off. PD-controller ICs like the LTC4267 use current limit and another feature, called «power good" to ensure the PD powers up properly. The controller's power good output keeps the rest of the PD's circuitry turned off until CIN charges to the port voltage. This is shown in Figure 3, where the LTC4267's PWRGD pin prevents its DC/DC converter from operating until there's less than 1.5V between VPORTIN and POUT. Using power good is very important with DC/DC converters as a converter providing constant output power will draw more current as its input voltage drops. If the converter turns on at a low voltage, its high current draw can slow or even prevent CIN from being charged. Consequently, power good or some other method of delaying DC/DC-converter turn-on is critical to the PD's successful powewer-up sequence.
Receiving power
Once the 50ms start-up time has expired, the PD's CIN should be charged to VPORT (less the 2 x VF of the diode bridge), and the PD's power consumption must be less than the maximum allotted to its class (Table 1). The PD must also signal its continued presence with a «maintain power" signature (MPS). If the MPS is absent, the PSE will turn off the power, preventing a powered cable from being plugged into Ethernet equipment that is not designed to accept power. The MPS is a DC current of 10mA or more and an impedance of less than 26.35k in parallel with more than 0.05µF. Very few PDs will need special circuitry to provide the MPS. In most cases, CIN, the impedance of the DC/DC converter and the current used for the PD's normal operation will meet the 802.3af MPS requirements. Energy Star-compliant and other very-low-power PDs like thermostats - where power dissipation can cause problems in the application - are allowed to pulse their MPS current above 10mA for 75ms with up to 250ms between pulses, reducing power to about 100mW. Like the MPS, in most cases staying within the class limits is handled by the PD's DC/DC converter and the circuitry drawing power from it. The designer must ensure the PD's circuitry always uses less than the class power in Table 1. The load circuitry cannot consume 12.95W because power is lost to the PoE interface (mostly in the diode bridges) and to the DC/DC converter. Using low-leakage Schottky diodes can reduce the losses in the diode bridges. In Figure 3, the LTC4267's PoE interface uses less than 180mW, and 200mW is lost across the 1.6Ohm RON MOSFET between VPORTIN and POUT, leaving 12.07W=12.95W-0.50W-0.18W-0.20W. How much of this 12W is available to the PD's circuitry depends on the DC/DC converter's efficiency.
Isolation
The most important aspect of the DC/DC converter in Figure 3 is the isolation between the input and output. Most PDs will need isolated DC/DC converters because the 802.3af standard requires that the pins in the Ethernet jack be isolated from any other conductive elements on the outside of the PD. An isolated DC/DC converter meets this isolation challenge, and the rest of the PD's circuitry can be designed without additional isolation.
Preparing for tomorrow
Almost as soon as the 802.3af Power-over-Ethernet standard was released, users were clamouring for more power. 13W is adequate for basic IP phones, but motorised cameras, multi-radio access points, and devices with large colour screens are seriously constrained. In response, the IEEE has formed a new study group, dubbed PoE+, that will develop a new standard to allow higher power devices to coexist with existing 802.3af devices available today. Although typical CAT 5 cabling includes four twisted pairs, the 802.3af standard only allows two pairs to carry current at any one time. One option is to allow additional current down the third and fourth pairs, doubling the available power. A second option is to raise the current limit, allowing more power down the same two pairs. Each of these techniques has appeared in proprietary PoE systems. However, each has drawbacks, complicating the choice between them. Utilising all four pairs has the potential of delivering the most power to the PD because it makes use of all the conductors in the cable, minimising the end-to-end resistance and the resulting power loss. However, powering all four pairs roughly doubles the cost of the port-controller circuitry, since a four-pair PSE must provide detection and fault control for each set of pairs. A four-pair PD, in turn, must limit the current draw from each pair set, and current balance must be maintained even when the incoming pair sets have significantly different voltages. The two-pair option avoids the cost and current-balance problems, requiring only minor modifications to the circuitry already in place in today's 802.3af designs. The cost for two-pair designs is the power lost when the cable gets long, since only half as many wires carry current compared to the four-pair case. This lost power causes heating of the cable, and adds to the stress on connector fingers and patch-panel traces. Above 30W, these factors can become significant. Higher current levels also aggravate ringnging due to parasitic inductance during plug and unplug events, increasing the risk of damage to PD or PSE circuitry. Any high-power scheme must remain backward-compatible with 802.3af systems. 802.3af PDs must plug into PoE+ PSEs and work normally, and when faulty, must be cut off at 802.3af levels for safety. PoE+ PDs must fail gracefully when plugged into 802.3af PSEs, either reducing those PSEs' capabilities to work within the limited available power or providing some indication to the user that they are plugged into the wrong type of PSE. Maximising the power available from a powered Ethernet port will enable new PoE applications, and a standard that takes full advantage of the infrastructure's capabilities will last longer than one that leaves room for ad-hoc solutions. Adding power while preserving the ease-of-use and consistent behaviour that made 802.3af a success is the challenge that PoE+ must meet..802.3af Classification Maximum PD Peak PD Class descriptionclasscurrentpowercurrent19 - 12 mA3.84 W120 mALow power PD217 - 20 mA6.49 W210 mAMedium power PD326 - 30 mA12.95 W400 mAHigh or full power PD
