The StarCore V5 architecture comes with 47 new instructions, which improve support for compilers and operating systems, enhance single-instruction multiple-data (SIMD) processing, and deliver highest-in-class multimedia and Viterbi performance. The V5 instruction set, built on StarCore's proprietary variable-length-instruction-set (VLES) technology, provides a unique combination of DSP performance and code density that's competitive with the most efficient microcontrollers. Relying on a fully-interlocked pipeline and branch-prediction logic, the StarCore V5 architecture maximises performance of compiled code and optimises high-frequency implementations with less costly memories. Thanks to a memory-management system, it is easy to support sophisticated operating systems such as Linux. The instruction set of the StarCore V5 architecture makes software-centric implementations of complex applications possible, eliminating the need for separate Viterbi and multimedia accelerators. In addition, removal of the programming restrictions that traditionally afflict DSPs makes using the V5 architecture as easy as programming a general-purpose microcontroller, claims the manufacturer.
