In a world where wireless communication operates at ever higher frequencies, analogue-to-digital converters are bound to follow the trend. Knowing that the sampling frequency of an ADC must be at least twice that of the signal frequency being sampled, and that the controller clock in SAR ADCs must even run at ten times this frequency, the technical challenges to achieve frequency conversion are increasingly high. Power consumption is a key factor tha puts pressure on the figure-of-merit (FOM) of advanced ADC technologies. It is defined as FOM = P/(2ENOB.FS), or the power consumption P divided by the product of the sampling frequency FS and two to the power of the effective number of bits. State-of-the-art commercial ADCs typically yield 1pJ per conversion step, and research results point towards 0.2pJ. The latter, however, do not always include the power consumed by the two major contributors to power consumption - the reference buffers and clock generation. The Belgian research centre IMEC has come up with a solution that improves this figure of merit to 0.065pJ per conversion step, including all contributions to the power consumption.
Back to the basics
Before diving into the details, let's first briefly go over the basic idea behind SAR ADC. The easiest way to understand its operation principle is by comparing it with a game where one must guess a number between, say, 0 and 100. By asking simple questions such as, "Is it larger than 50? If yes, is it larger than 75? etc.", you make a stepwise approach towards the value you need. In the most straightforward ADC configuration, the input signal is compared to a reference voltage (Vref) generated by voltage division in an appropriately switched binary-scaled capacitor array (that is, an array with declining capacities). Comparing the input signal consecutively with each voltage allows with each step to determine one bit of the binary code you are looking for. In terms of algorithms, you roughly need one step to sample the input signal and reset the comparator, a second step to hold the input signal and set the capacitors to the reference and finally a number of cycles equal to the number of bits for the conversion itself.When transforming this principle into a reality with - for example - a 50Msample/s sampling rate, ADC designers are left with about 2ns for each conversion step in a 9-bit word. Charging and resetting the circuit in this flick of time would require an enormous buffer on your Vref. This, combined with the high-speed clock needed to steer the cycling, results in unacceptable power consumption.
Removing the bottlenecks
IMEC therefore looked at these two most critical parameters to develop an entirely new low-power architecture. Instead of the active charge redistribution used in the capacitor arrays of conventional SAR ADCs, the novel concept uses passive charge sharing to sample the input signal and to perform the successive-approximation cycling. The SAR operation is no longer done based on voltage comparisons, but operates completely in the charge domain (see Figure 1). In a first step, a charge proportional to the input signal is charged onto a capacitor. During the successive approximation algorithm, reference charges are added or subtracted until the result converges to zero. To add and subtract charges, simple passive switches are used instead of the active circuits needed for charge redistribution in conventional SAR ADCs: the only active elements left in the IMEC architecture are the comparator and the digital controller. Since the charge sampling itself is also performed in a passive charge-sharing action between two capacitors, thereby only depending on the on-resistance of the switch, the sampling time is very short - typically less than 2ns. The reference capacitors are all pre-charged to the power supply before the actual conversion; moreoever, this operation requires no fast op-amps and considerably relaxes the requirements on the buffer. The largest fundamental power constraint is thereby removed.To avoid the second largest power contribution (the need for a high-speed clock that controls the SAR algorithm), an asynchronous controller is implemented. Each time the comparator gives the output signal "valid", another iteration step is automatically triggered. After 9 steps (in a 9-bit ADC), the output bits are toggled, the sampling capacitors reset and the references pre-set, and all will be waiting for the next input signal. The total conversion time is 20ns, making the maximum conversion rate 50Msample/s.While this simplified description mentions the major r adaptations in the IMEC architecture, it leaves out a number of subtleties also contributing to the final result. For example the comparator is constructed in a way that it consumes no power in the inactive mode. Its power consumption therefore scales linearly with the sampling frequency and helps maintaining the figure of merit down to very low conversion rates. All things considered, the IMEC SAR ADC (Figure 2) outperforms all state-of-the art commercial ADCs by a factor of 10: this is 3.7 times better than ADCs described in literature in the same process generation (90nm) and 2.5 times better than any high-speed research ADC.
