Synopsys has introduced IC Compiler 2007.03, the next generation place and route solution. The 2007.03 release heralds significant advances in IC designer productivity through faster runtime, higher capacity, smarter multi-corner/multi-mode (MCMM) optimisations, and improved predictability. The release also rolls out physical design support for the emerging 45nm technology wave.
With greater than $100 million in cumulative customer orders and nearly 100 active customer designs, IC Compiler is increasingly the choice for market leading IC designers in a broad class of applications and across a wide silicon technology spectrum.
"2007.03 is the most significant release of IC Compiler yet, delivering strong advantages for a large group of users," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "The release provides advances in core technology, benefiting users across the board. It also delivers improved productivity through higherautomation in key functions such as MCMM optimisations and signoff driven timing closure."
IC Compiler 2007.03 introduces new technology for a fast operating mode which can deliver 35 percent runtime improvement without trading off quality of results. Coupled with improved capacity approaching 10 million gates on 16GB platforms, this new technology allows users totake on larger block partitions.
The release adds early access to integrated hierarchical design planning, enabling users to efficiently tackle designs in the 100 million gate range. Another key productivity enhancing capability is the physical feasibility flow, which allows users to quickly generate and analyse multiple trial floorplans to determine the right starting point for detailed implementation.
For advanced designs, IC Compiler 2007.03 introduces Adaptive MCMM optimisation technology, which delivers faster runtime and smaller memory utilisation while providing the same level of accuracy. IC Compiler's approach to implementing truly concurrent optimisation for designs with multiple modes and corners is an immense advantage for advanced users.
These users cannot afford the scheduling impact of sequential optimisation or accept the less accurate merging technique employed by other place and route tools. The advanced designs also benefit from IC Compiler's signoff driven timing closure which is now available as a production capability.
For emerging 45nm designs, IC Compiler 2007.03 provides early support to leading edge customers in the form of 45nm placement and routing design rules. It also meets the new requirements for lithography compliance and chemical mechanical polishing related metal uniformity.
Today, Synopsys is partnering with major semiconductor vendors worldwide to ramp production support for 45nm design implementation. As with 90nm and 65nm designs, Synopsys' physical implementation solution is the first in enabling tapeouts at 45nm.
About IC CompilerIC Compiler is Synopsys' next-generation place and route system. It provides superior results and faster time to results by extending physical synthesis to full place and route, and by enabling signoff driven design closure. Previous generation solutions have a limited horizon because placement, clock tree, and routing are separate, disjointed operations.IC Compiler's Extended Physical Synthesis technology breaks down the walls between these steps by extending physical synthesis to full place and route. IC Compiler has a unified, TCL based architecture that implements innovations and harnesses some of the best Synopsys core technologies. It is a complete place and route system with everything necessary to implement next generation designs, including physical synthesis, placement, routing, timing, signal integrity optimisation, power reduction, design for test, and yield optimisation.