Mentor Graphics has announced immediate availability of the Olympus-SoC platform with new features for low-power IC implementation. The place-and-route system is designed for today's large, complex low-power SoCs with the ability to directly handle 100 million-plus gates in flat mode. Fully-multi-threaded analysis engines and the industry's only fully-parallelised timing and optimisation engine provide up to seven-fold speed-up on multi-core and multi-CPU computing platforms, claims the company. It is based on the design-for-variability Olympus-SoC architecture that natively optimises for variations in design modes, process corners and manufacturing. A flexible architecture for automated multi-voltage design flow has been introduced as well as advanced techniques for power reduction in complex clock trees. Automated multi-voltage flow with support for dynamic voltage and frequency scaling handles varying supply voltages and clock frequencies, as well as special cells such as level shifters and isolation cells. It also includes concurrent optimisation of leakage and dynamic power, timing and signal integrity across MCMM (multi-corner multi-mode) scenarios. Multi-voltage design, a mainstream technique to reduce total power, is a complex, time-consuming task as many blocks operate at different voltages—or intermittently shut off—thus increasing the number of power states, which compounds the MCMM problem. Power consumption in the clock-tree network is a significant portion of the total chip power, which demands power-aware clock-tree-synthesis solutions for increasing wire resistance and resistance variability at smaller geometries. Moreover, design tools have to handle increasing design sizes with more functionality, which can lead to the designer having to divide the design into manageable pieces, thus complicating top-level chip assembly closure. A unified-power-format-based Netlist-to-GDSII flow includes support for power-state-definition tables. Concurrent multi-Vt optimisation, power gating using MTCMOS switch cells and power-aware buffering and sizing features are also integrated in the platform.
