Altera has introduced a low-power family of FPGAs with security features. The Cyclone III LS series is based on the company's Cyclone III architecture, has 8.2Mbit RAM, 396 multipliers and 200k logic elements, and is manufactured using TSMC's 60nm low-power process. The largest family member delivers 0.25W of static power consumption, which is a 10 to 20% reduction, claims the company, with the reduction from the 65 to the 60nm node. The FPGAs are designed for use in applications where there are power and board restraints. New features for the Cyclone architecture are the 256AES encryption key, which had previously only been available in Stratix devices. It protects the bitstream with encryption so that reading from the flash device to the FPGA is not possible. There is JTAG-port protection, tamper monitoring and cyclic redundancy check to protect sensitive information. The on-chip oscillator can detect a user-defined tamper event, such as an attempt to read the FPGA, and will not clock the external clock source. A new feature is the ability to erase the memory and set all the bits to zero if there is a tamper event detected. There is also single-chip redundancy in hardware and software, where the parts are physically separated. Physically separated redundant design may be a requirement in some military/high-reliability applications so that two encrypted or unencrypted pieces of data can be processed without fear of "contaminating" the same device. This approach is also used in software-designed radio, where multiple channels in a single device are required but with a small footprint and the low-static-power requirements of a single-channel device. As well as military use, the FPGAs are suitable for use in industrial Ethernet, motion control and industrial safety.
