TSMC has unveiled a commercial 65nm MTP (multi-time-programmable) non-volatile-memory process technology, which incorporates process-qualified MTP IP blocks jointly developed with Virage Logic. The new technology is the first 2.5V MTP process, breaking the 3.3V baseline barrier. It eliminates the need for an external EEPROM—currently required in many systems applications—thereby reducing power, area and costs while increasing data security. The process is built with up to 10 metal layers using copper low-k interconnects and nickel silicide transistor interconnects. It is logic-compatible, and the memory requires no additional processes or masks. Devices built using the process will support full read and program operations across temperatures ranging from -40 to +125°C, with minimum 10-year data retention at +125°C. Built on the foundry's 65nm Low Power process, the MTP technology features a memory size of up to 8kbit, which is suitable for small memory requirements associated with MP3 downloadable digital-rights management, RFID devices, fingerprint-identification applications, and pre-paid cash or phone cards. The process is suitable for cellular baseband, as well as portable applications and multimedia processors. The company's 65nm General-Purpose process targets graphics, networking and high-end ASIC fabrication, while the high-speed process is intended for CPU and advanced graphics processors.
