Rambus has unveiled its Mobile XDR memory architecture for next-generation mobile products, which includes Mobile XDR DRAM, Mobile XDR memory controller PHY, or MIO, and the Mobile XDR memory controller, or MXC. The Mobile XDR memory architecture will enable future mobile memory platforms which can achieve throughputs of up to 4.3Gbit/s/pin with unequalled power efficiency. With this performance, SoC platforms can achieve over 17Gbyte/s of memory bandwidth from a single DRAM device. It is also claimed to extend the battery life of many mobile products by more than 30minutes, when operating under power-hungry usage profiles. The architecture reduces pin-count reduction and the interface. Power reduction is achieved through a decrease in active power coupled with fast transition times to power-saving modes to minimise memory sub-system power in applications from simple applications, for example, voice transmission to complex multimedia ones such as stereoscopic 3D HD video. The architecture uses VLDS (very low-swing differential signalling). FlexClocking uses asymmetric partitioning and places critical calibration and timing circuitry in the SoC interface, simplifying the design of the DRAM interface. The advanced power state management reduces memory system power and provides ultra-fast transition times between various low-power and active operating modes.
