Altera claims it has broken through the "bandwidth barrier" with the 28nm Stratix V FPGAs. The GX version, the first device available, supports applications with 600Mbit/s to 12.5Gbit/s transceivers. The GT version is claimed to be the industry's only FPGA with integrated 28Gbit/s transceivers and is targeted at 100G systems and beyond. The GS version is optimised for high-performance DSP applications with 600Mbit/s to 12.5Gbit/s transceivers. Finally, the E version is the highest density and is suitable for ASIC prototyping, emulation or high-performance computing applications. The FPGAs offer up to 1.6Tbit/s serial switching capability and provide up to 1.1million logic elements, 53Mbits of embedded memory, 3,680 18x18 multipliers and integrated transceivers operating at up to 28Gbit/s, setting a new benchmark in the industry. The devices feature the company's Embedded HardCopy Blocks to provide the equivalent of 700K additional logic elements with 65% lower power compared to a soft logic implementation. The GX and GS models feature up to 66 high-performance, low-power transceivers operating up to 12.5Gbit/s. All FPGAs support and meet compliance 3G, 6G and 10G protocols and electrical standards such as Interlaken and PCI Express. The devices also provide direct interoperability. An adaptive logic module architecture adds up to 800k registers. Parital reconfiguration allows designers to reconfigure part of the FPGA while other sections remain running.
