A fabless ASIC company, based in Taiwan has addressed the power consumption challenges posed by the proliferation of devices like the iPad, smartbooks and e-books, with a low power design flow and virtual IDM, claimed to be more efficient that traditional IDM. Global Unichip's PowerMagic low power design reduces leakage power with external power shutdown and customised low leakage I/O and power gating using coarse grain MTCMOS and rush current analysis with multi-VT libraries. To reduce dynamic power it uses multiple voltage library characterisation and voltage islands, with level shift insertion. The PowerSlim library is claimed to deliver a 25 to 50% reduction in typical leakage power and 10 to 15% reduction in typical dynamic power. The company claims that Janus is the world's first ESL design service. It allows engineers to perform macro and micro architecture exploration and verification without having to remodel legacy IP in SystemC and TLM 2.0. Instead, developers can use a standard OSCI environment to develop SoC and IP and co-emulated with legacy RTL and ARM926EJ. Functional models developed in C and C++ can verify RTL implementation using an FPGA. The regression test runs x200 faster than RTL simulation, according to the company. At the GlobalPress Summit, in California, the company announced a 50million gate, 65nm SoC with 200Mbut SRAM, 3.125GHz SerDes and xaui interfaces and 3.125Gbit/s operation.
