Synopsys has introduced the DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards. The Universal Memory Controller helps reduce both the latency and silicon area by up to 50% compared to the company's previous generations of DDR memory controllers, thus improving the DRAM interface performance and reducing overall chip costs. The controller provides efficient DDR control and protocol translation for applications without the need for a multi-ported memory controller. Both controllers deliver memory system performance of up to 2133Mbit/s, the maximum data rate of the DDR3 standard, and offer a DFI 2.1-compliant interface to the DDR PHY. The controllers enable designers to easily integrate multiple DDR interfaces into one design, servicing a range of products spanning applications such as consumer electronics, mobile, network computing and automotive with less risk and improved time-to-market.
The multi-port Universal DDR Memory Controller accepts memory access requests from up to 32 application-side host ports, each of which can be configured independently to be synchronous or asynchronous to the controller clock. The Universal DDR Memory Controller provides greater memory bandwidth utilisation through transaction reordering, bandwidth allocation per port, and quality-of-service-based arbitration for latency-sensitive and/or high-bandwidth traffic.
Complementing the Universal Memory Controller, the advanced single-port Universal DDR Protocol Controller is designed to optimise memory channel bandwidth utilisation with reduced latency, allowing designers to implement a custom memory scheduler that is optimised for specific DRAM traffic patterns. The Universal DDR Protocol Controller supports 1:1 or 1:2 clock frequency ratios between the controller and memory channel, enabling low latency in high speed, general purpose process technologies, and ease of timing closure in low-power process technologies.
