Synopsys has introduced the IC Compiler 2010.03, a physical implementation solution delivering high performance on MCMM (multi-corner/multi-mode) designs, and enhanced In-Design technology for fast design closure. The software's In-Design technology helps prevent late-stage surprises by enabling signoff-accurate static timing analysis, rail analysis and physical verification during design. The new software release has production support for all known 28 and 32nm design rules for major foundries, with several customer tapeouts underway.
The software offers performance improvements across the board when compared to the previous solution. It provides 2X faster time to initial floorplan creation and on-demand loading, which offers 2X to 3X faster time to final floorplan creation. The software also includes 2X faster pre-route feasibility engines and generates interactive reports that help significantly reduce iterative cycles during early stages of design. Faster MCMM scenario processing, core engine improvements and multimode clock tree synthesis deliver faster timing convergence.
Traditional implement-then-verify approaches result in lengthy design iterations due to late-stage surprises. The software's In-Design technology reduces such iterations by enabling signoff accurate analysis and physical verification during design. In-Design enhancements in the new release include dynamic rail analysis with PrimeRail and DRC auto fixing with IC Validator. The software introduces a new leakage optimisation engine capable of handling more than 20 leakage variants. This is achieved by using In-Design technology with PrimeTime to deliver considerable leakage reduction while preserving signoff timing. This capability, combined with advances in post-route leakage optimisation and MCMM leakage scenario optimisation, enables the software to deliver double the leakage savings in half the time.
The software is available today and includes a quad-core license enabling multi-core processing as a standard feature.
