Fujitsu Semiconductor Europe has released it second generation 8bit charge-mode Interleaved sampler (CHAIS) ADC for optical transport designs based on coherent detection. It supports data rates from 55 to 65Gsample/s and is based on the same architecture as the company's 56GSample/s CHAIS ADC in 65nm. It offers ultra-fast sampling rates, wideband input, low noise and high resolution, all of which are necessary for long-haul links with data rates of 100Gbit/s and higher, over a single wavelength. Implemented in a 0.9V 40nm CMOS technology, the ADC architecture allow for scalability to sampling rates of 400Gbit/s or 1Terabit/s, for future transport data rate. Typical power dissipation for a single channel in 40nm is only 1.2W, which is a reduction of 50% from the power/ channel in 65nm, says the company. The four-channel CMOS design allows for more efficient integration with coherent receiver digital cores, typically comprising tens of millions of logic gates and a multi-terabit data transfer rate across the interface between core and ADCs. For single-die transceiver SoCs in 40nm, the company offers high speed 11Gbit/s SerDes IP and supporting protocols. Electronica: Hall A6: stand 313
