Xilinx claims that it has developed the industry's first stacked silicon interconnect technology allowing multiple FPGA dies to be used in a single package. Until its introduction, one disadvantage to integrating silicon onto a PCB or multi-chip module is that it can adversely affect the connectivity. The logic per I/O can be so large that it is difficult to get the logic on and off the chip quickly enough. The Stacked Silicon Interconnect technology has been added to the company's 28nm Virtex-7FPGAs to offer up to 2million logic cells. Software support is ISE Design Suite 13.1,which is available to beta customers. The 28nm Virtex-7 LX2000T device will be the world's first multi-die FPGA and provide more than 3.5 times the logic capacity of the largest current-generation 40nm FPGA with serial transceivers from the company and 2.8 times the logic capacity of the largest competing 28nm FPGA with serial transceivers. The device uses micro-bump assembly, through-silicon via technology, and silicon interposer architecture and TSMC's low power consumption, 28nm HPL process and circuit board technology. The via and silicon interposer structure create the stacked silicon interconnect which allows data flows between adjacent FPGA die across over 10,000 routing connections. This approach is in contrast to using standard I/O connections to integrate two FPGAs on a circuit board and it is claimed to provide over 110 times the die-to-die connectivity bandwidth/W at 20% the latency without consuming high-speed serial or parallel I/O resources. Having the die next to each other and interfaced to a ball grid array is claimed to avoid the thermal flux that can be found with a vertical die-stacking approach, says the company. The technology's ultra high-bandwidth, low-latency and low-power interconnect allows customers to implement applications applying the same approaches used for large monolithic FPGA devices, using the software's built-in auto partitioning capabilities for push-button ease-of use, or using hierarchical and team-based design techniques. Initial devices will be available in the second half of 2011.
