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BiCD Process For Integration
features enhanced power-handling capability
08/12/2010
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Toshiba Electronics Europe has revealed details of its BiCD process, which combines 130nm logic design rule with current-handling capability to permit integration in devices such as sensor-less BLDC motor drives. The process offers full specification over a wide temperature range and features high ESD robustness, providing a platform for industrial and automotive IC projects. The process combines Bipolar, CMOS and LDMOS base technologies with deep trench isolation. This causes high voltage capability up to 60V with reduced leakage currents, especially at high temperatures. By achieving low on-resistance (RDS(ON)A), 32mΩ. mm2 for 40V, 70mΩ. Calculated mm2 for 60V, the process delivers enhanced power-handling efficiency and integration of control and bus-interface functions using its 130nm CMOS technology. Supporting the process, the company also has high-density power package technologies such as heatsink QFP, QFN, and WCSP engineered to withstand the automotive environment.


Toshiba Electronics Europe GmbH

Hansaallee 181
40549 Düsseldorf - Germany -
tel: +49 211 5296 0
fax: +49 211 5296 400

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May 2012