Altera has released the Quartus II development software version 10.1. The Quartus II Subscription Edition software for CPLD, FPGA and HardCopy ASIC design includes the availability of a beta version of Qsys, the company's next-generation system-integration tool, which features the industry's first FPGA-optimised network-on-chip-based interconnect. The tool offers memory-mapped and streaming interface support that achieves nearly double the performance of the company's SOPC Builder tool. The software applies network theory to on-chip communications that provide performance improvements over conventional bus and switch fabric interconnections. Packetising all memory-mapped and streaming data delivers higher operating frequency for the same latency and resource use, says the company. There is also automatic pipelining feature to increase system fMAX. Designs that include a high number of IP or system components benefit from the hierarchical design flow. The tool enables system scalability by dividing large FPGA designs into multiple sub-systems. This hierarchy allows designers to manage each sub-system with the ability to add extra sub-systems to the design with minimal impact on system performance. The tool automatically handles the bridging between multiple interface standards to leverage IP cores with multiple interfaces in a single design. The initial release supports the Avalon interface.
