The immediate availability of the HiGig MAC IP core for low cost LatticeECP3 FPGA family has been announced by Lattice Semiconductor. Multiple individual devices interconnected via the HiGig protocol operate as one logical network, seamlessly providing features like quality of service, mirroring and link aggregation. The IP core ensures that the Media Access rules specified in the 802.3ae IEEE standard and HiGig protocol definitions are met while transmitting a frame of data over Ethernet. On the receive side, it extracts the different components of a frame and transfers them to higher applications through a FIFO interface. With this IP core, designers will be able to implement low cost network solutions using Broadcom devices. Compliant with Broadcom HiGig and HiGig2 protocol definitions, the IP core has a 64bit wide internal data path operating at a maximum frequency of 156MHz on the LatticeECP3 FPGA. The core provides XGMII and XAUI interfaces to the PHY layer and supports variable-sized packet transmission with fixed-sized messaging capability (HiGig2 only). With multi-cast address filtering and 16bit statistics counters, the core requires approximately 4100 FPGA look-up tables for HiGig implementations and approximately 4700 FPGA LUTs for HiGig2 implementations.
