PMC-Sierra's SynthePHY dual-channel 6Gbit/s SerDes and programmable clock synthesisers are optimised for wireless infrastructure radio designs. They allow 30 clock outputs to be programmed over a frequency band of 3MHz to 1.6GHz and meet the phase noise performance required by multi-carrier GSM, WCDMA and LTE systems. The devices support CPRI, OBSAI, and IR remote radio unit designs and are programmable from 614.4Mbit/s to 6.144Gbit/s data rates. They can be used to drive cable, backplane or optical modules to share a common radio design for rack-mount and remote radios. There are 18 differential low voltage 50Ω drivers with programmable output levels and phase control. Clock rates up to 1.6GHz are supported. Each device has 12 single-ended LVCMOS drivers with programmable divider and phase control, and supports clock rates up to 307.2MHz. Integrated jitter below 200fs and phase noise floor also below 160dBc/Hz on 1GHz differential output clocks and 250MHz LVCMOS output clocks can be achieved using a low-cost VCXO reference. The PM7501 features dual 6Gbit/s SerDes; 18 differential and 12 LVCMOS outputs in a 3x13mm, 225-lead, 0.8mm pitch flip chip CSP. The PM7520 SyntheCLK features 18 differential and 12 LVCMOS outputs in a 12x12mm, 196-lead, 0.8mm pitch flip chip CSP. Both operate from -40 to +85°C.
