Lattice Semiconductor will show its MachXO2 family of infinitely reconfigurable PLDs which offer designers of low density PLDs a mix of low cost, low power and high system integration in a single device, claims the company. The PLDs deliver a three-fold increase in logic density, a 10 fold increase in embedded memory, more than a 100 times reduction in static power and up to 30% lower cost compared to the earlier generation. They have a user flash memory, I2C, SPI and a timer/counter and can be used in system applications (telecomms infrastructure, computing, high end industrial, high end medical) and consumer applications (smartphones, GPS devices, mobile computing, digital cameras). The LatticeECP3 family (pictured) will also be featured. These third generation, mid-range FPGAs offer the industry's lowest power consumption and price of any SerDes-capable FPGA device, claims the company. They offer multi-protocol 3.2G SerDes with XAUI jitter compliance, DDR3 memory interfaces, DSP capabilities, high density on-chip memory and up to 149k LUTS. The company's Platform Manager will also be in Nuremberg. The mixed-signal devices simplify board management design by integrating programmable analogue and logic to support common functions, such as power management, digital housekeeping and glue logic.
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