JTAG Technologies has enhanced the performance of its ProVision suite of boundary-scan development tools with the addition of 11 enhancements. The first of these is the addition of all instructions handling (including private instructions) within ProVision's JTAG Functional Test (JFT) capability, now giving users easier access to device registers; other than just those needed for IEEE Std. 1149.1boundary-scan operations. Registers needed to invoke on-chip emulation modes and programming registers can now be accessed using JFT's Python routines. A ‘netlist type autodetect' has been added which automatically recognises netlist formats as belonging to their respective tool vendors. This can save considerable time when importing netlists from third parties. Thirdly, the WGL test vector format (as used for IC testing) is now supported through a ProVision plug-in. The fourth enhancement is the ability to test (IEEE) 1149 dot 6 to dot 1 connections. The remaining seven enhancements are: 5) support for FTDI USB to serial port peripheral devices (embedded on target board); 6) HTML reporting for TTR and BSD in AEX sequences; 7) the ability to export and re-import AEX sequences; 8) support for double-latching bus logic; 9) boundary-scan register length check; 10) support for multiple ID codes in BSDL; and 11) 64-bit drivers for DataBlaster hardware
