Tensilica has launched the ConnX BBE64-128 DSP IP core for SoC design. It provides over 100 GigaMACs performance in 28nm to meet the performance of LTE Advanced handsets. The DSP can perform at 128 MACs/cycle for maximum throughput and minimum energy for most common MIMO and channel estimation functions. It is based on a multi-slot, very long word architecture across many applications with dense code and power efficiency. The DSP has soft bit vector data types and operations including arbitrary field insertion and extraction for complex transmit operations. It incorporates a single-cycle, 16-way complex radix-4 and radix-8 FFT and discrete Fourier transform for arbitrary size transformations common to OFDM algorithms. Accelerated interleaving is for all bit, byte, half-word and word vector types for flexibility and efficiency in hybrid automatic repeat request, FEC and convolutional coding.
