Lattice Semiconductor has announced full support for Aptina's HiSPi (high-speed serial pixel interface) using LatticeXP2 FPGAs. The LatticeXP2 HiSPi bridge reference design allows any ISP (image signal processor) with a traditional CMOS parallel bus to interface with an Aptina HiSPi CMOS sensor. This solution is suitable for security cameras, automotive applications, and high end consumer cameras where the use of high resolution and high frame rate CMOS sensors is desirable.
The bridge reference design supports all modes of the HiSPi specification. The FPGA supports one to four data lanes up to 700Mbit/s. HiSPi formats of packetised-SP, streaming-SP, streaming-S or activestart-SP8 are also supported. The HiSPi bridge also provides support for sensors in linear or HDR mode. The parallel bus interface to the ISP is configurable from 10 to16 bits and the voltage level can be set from 1.8 to 3.3V.
