Designed with the aim of helping SoC designers take advantage of the performance gains of the DDR4 memory standard, Cadence Design Systems has announced DDR4 technology. The EDA company claims that DDR4 is an important memory controller interface as it has IP and an integration environment that is required to speed integration, reduce cost and ensure design manufacturability. The interface includes hard and soft PHY IP; controller IP; memory models; verification IP; tools and methodologies; and signal integrity reference designs for the package and board. The DDR4 specification is an evolutionary SDRAM memory technology standard currently under review at JEDEC. It proposes speeds ranging from 1600 to 3200Mtransfers/s, more than 50% faster than the current DDR3 standard. According to the company, the integration environment enables customers to model and analyse the target memory topology, and verify the behaviour of the IP at both the SoC and system levels. The soft PHY and controller can be synthesised to support a range of frequencies and voltages, claims the company. Designers can deliver either a pure DDR4 SoC, or combine DDR4 with technologies such as DDR3 or LPDDR2. The company expects vendors in the networking and enterprise markets to begin designing equipment using DDR4 in 2012.
