Lattice Semiconductor has announced the availability of a 4 x 3.125Gbyte/s version of the SRIO (serial rapid IO) 2.1, Level 1 endpoint core utilising the LatticeECP3 FPGA family. This is an extension of the SRIO v2.1 core that supported 1x and 2x up to 3.125Gbyte/s and 4x up to 2.5Gbyte/s.
According to the company, the SRIO allows for 1x, 2x and 4x lane configurations, supports up to 3.125Gbyte/s, implements physical layer, transport layer, maintenance transaction handling and error management extensions, provides infrastructure support for external logical layer functions, provides a choice of how logic layer functions interact with the rest of the system - SoC bus or streaming interfaces, supports software implementations of control plane-oriented functions such as doorbells and messages and is backward compatible with the v1.3 specification.
