Evatronix has introduced a USB High Speed PHY IP that complements the company's existing USB 2.0 device and host controllers. The IP is silicon proven and complies with all relevant layers of USB specification for high, full and low speeds. It is a mixed-signal transceiver macro-cell that implements the USB 2.0 physical layer for host and device applications. The PHY IP is compliant with the UTMI+ specification and features a built-in self test, self calibration termination and pull-up resistors. It also supports 3.3V analogue and 1.8V digital core supplies. The company claims that the PHY enables designers to tailor the device to the needs of a particular application. The PHY's logic macro is available in the LFoundry 150nm process and can be ported to any technology node from 45 to 180nm.
