MathWorks has announced that the Simulink Design Verifier 2.0 includes polyspace analysis technology for automated error detection in simulink models. Design verifier integrates polyspace error detection and that can reduce the time required to find and fix the root cause of design errors, and hence decreasing the overall cost of verification and validation, claims the company. The features of the verifier include detecting the dead logic, integer and fixed-point overflows, division by zero, and assertion violation, blocking and functioning of modeling functional and safety requirements, generating test vector from functional requirements and model coverage objectives, property proving with generation of violation examples for analysis and debugging and fixed-point and floating-point model support.
