IC design service company, EnSilica and Evatronix, the Polish silicon IP provider, have collaborated to produce eSi-RISC processor SoCs incorporating USB 1.1, 2.0 and 3.0 connectivity. The IP, including support for USB OTG, has been integrated into the eSi-SoC Generator tool, which automatically produces processor sub-system RTL including bus arbitration. Depending on customers' system level requirements, support is provided for low speed, full speed, high speed and SuperSpeed devices. (The new SuperSpeed standard supports data rates up to 5Gbit/s.) The IP is configurable, allowing hardware resources to be optimised to the performance requirements of the end application. These include parameters like the number of end-points and options dedicated for USB DMA engine support. Suspend and resume power management functions are supported reducing the overall system power. A USB software stack, with mass storage class option, provides everything required to deploy a low-cost USB processor sub-system reducing risk, cost and time to market for customers. The USB IP is certified by the USB-IF. The USB IP coupled with eSi-Connect peripherals provide processor sub-systems without engineers have to integrate hardware and software IP from different sources. Peripherals available include cache and static memory interfaces, DMA and encryption accelerators.
