Altera has rolled out the Stratix V GX FPGA signal integrity development kit, featuring 28nm FPGAs. According to the company, this kit allows measuring and evaluating transceiver link performance ranging from 600Mbyte/s to 12.5Gbyte/s. The kit features equalisation functions for high-speed serial transceivers. Real-world system analysis can be performed using on-board SubMiniature version A and backplane connectors including Molex Impact and Amphenol XCede. These built-in, high-speed backplane connectors are used to evaluate custom backplane performance and evaluate link bit error rate. Patterns of PRBS (pseudo-random binary sequence) can be generated and checked via a GUI, says the company. The kit allows verification of compliance with protocol standards including 10GbE, 10GBASE-KR, PCI Express Gen1, Gen2 and Gen3, Serial RapidIO, XAUI (10Gb attachment user interface), CEI-6G (common electrical I/O-6G), CEI-11G, HD-SDI (HD-serial digital interface), Interlaken and fibre channel. The development kit features a Stratix V GX FPGA-based development board, a one-year license of Quartus II software, design examples and access to Altera's MegaCore IP library including the Nios II Embedded Design Suite.
