Inphi has announced the low power 100GbE CMOS PHY solutions that support the IEEE 802.3ba standard and target next generation high density 100G line cards, says the company.
By integrating multiple channels along with transmit and receive functions on a single IC, the company can double the levels of integration available from existing 100GbE PHY and CDR offerings, claims the company.
The iPHY IN112510 is a single-chip, low-power PHY for 10:4 GB (gearbox) applications for 100GbE and OTU4 high-density 100Gbit/s line cards with 25 to 28Gbit/s electrical interfaces. It supports 100G BASE-LR4/ER4 and OTU4 28Gbit/s operation for OTL4.4. The PHY also features programmable transmit and adaptive receive equalisation on all SerDes interfaces with fine granularity and control which allow performance to surpass IEEE CAUI, CEI-11G SR and CEI-28G VSR specifications.
The iPHY IN012525 is a low-power CDR (clock data recovery) for 100GbE and OTU4 next generation 100G modules. This CDR supports 100G BASE-LR4/ER4 and OTU4 28Gbit/s operation. It features programmable transmit and adaptive receive equalisation on all SerDes interfaces with fine granularity and control which allow performance to surpass CEI-28G VSR specifications.
The chipsets feature self-test modes that allow diagnostic monitoring of channel and system parameters and eye-scan and monitor on all SerDes receiver interfaces for link margin and stress testing in a lab or production test environment. The chipsets are suitable for data center and enterprise networks.
The company also announced the IN2841TA, a TIA (transimpedance amplifier) and LIA (limiting amplifier) for 100GbE receivers. Interoperable with the company's iPHY 100GbE CMOS SerDes solutions, the company's IN2841TA offers the low power, good sensitivity, and high overload, according to the company. Together, the IN2841TA and iPHY CMOS SerDes create a platform solution for 100GbE CFP and CFP2 modules.
