Using technology that was announced last year, Xilinx has shipped the first Virtex-7 2000T FPGAs, claiming that they are the world's highest capacity PLD. The devices are the first to use Stacked Silicon Interconnect (SSI) technology and with micro bump fine pitch connectors which are claimed to have 16 to 25 times the density of conventional bumps parts. The single monolithic chip is part of the company's mission to deliver an alternative to large, 20million gate ASICs and to halve the current ASIC development time of two years. The FPGA is built using 6.8 billion transistors, providing access to two million logic cells, or equivalent to 20million ASIC gates. It can replace large capacity ASICs to achieve comparable costs in a third of the time, claims the company and to create integrated systems that increase system bandwidth and reduce power by eliminating I/O interconnect, and accelerating the prototyping and emulation of advanced ASIC systems with the ability to reprogram. According to the company, SSI outpaces Moore's Law, offering twice the capacity that could otherwise be available in a monolithic 28nm FPGA. The die align side by side on a silicon interposer which avoids the power and reliability issues incurred by stacking multiple dies on top of each other. The interposer includes over 10,000 high speed interconnects between each die. Liam Madden, corporate vice president, FPGA Development and Silicon Technology, Xilinx, explained that the increased capacity allows developers to add new functionality to existing designs, without the ASIC stage in the development; or reduce a three or five FPGA design into a single device. It can also allow prototyping and building system emulators 12 months sooner than is typical for a new generation of devices, as SSI builds the PLD from four separate FPGA die interconnected upon a passive silicon interposer.