Redefining its ECP3 FPGA family, Lattice Semiconductor has introduced the ECP4 FPGAs which are believed to be the first 6Gbit/s SerDes devices in the economical wire bond packaging. They are also available in flip chip packages depending on whether used in a chip to chip or long haul backplane application. The six FPGAs target power sensitive wireless and wireline, video and computing applications with the inclusion of DSP blocks with 18x18 multipliers which can be split into 9x9 formations or combined into 36x36 as required. Multipliers can also be cascaded to create filters for remote radio heads, MIMO-based RF antennae and video processing. The FPGAs also include hard IP-based communication engines. The FPGAs contain up to 16 SerDes channels with embedded physical coding sub-layer blocks. The communication engines support PCI Express 2.1, multiple 10GbE MAC, tri-speed Ethernet MACs and SRIO 2.1. According to the company, the FPGAs are up to 50% faster than earlier devices and have 1066Mbit/s DDR3 memory interfaces and 1.26Gbit/s I/Os that can be provisioned as serial GbE interfaces. There is 66% more logic and 42% more embedded memory than the earlier family. Samples will be available early 2012. The first device in production will be the ECP4190, with 12 SerDes channels and 36 1.25Gbit/CDRs with 183k LUTs, 5.9Mbit embedded memory, 480 DSP block 18x18 multipliers, three comms engines and up to 456 I/O.
