Tektronix has added software capabilities for its TLA7SA08 and TLA7SA16 Logic Protocol Analyser Modules supporting PCI Express (PCIe) 3.0, the next generation PCIe specification. Designed to make PCIe system debug and analysis faster and easier, the new capabilities include an innovative Bird's Eye View (BEV) to help engineers visualise and investigate difficult flow control problems along with one-click calibration and auto configuration. Featuring double the data rate and improved I/O bandwidth over previous generations, PCIe 3.0 specifications bring new complexity and testing challenges in both the physical and the protocol layers. Further, PCIe is designed to be used in a wide variety of applications, putting pressure on test instruments to track features such as dynamic link width change, dynamic speed change, lane ordering, polarity changes and several power saving modes. Bird's Eye View offers a completely new way to visualise information to quickly investigate PCI Express flow control problems which can be some of the most challenging issues to debug. The Transaction Window, a single innovative window on the Tektronix Logic Protocol Analyser, provides views of protocol behavior at the packet and transaction level interspersed with physical layer activity. One-Click Calibration combines the Logic Protocol Analyser's acquisition hardware and trigger capabilities to exhaustively test hundreds or even thousands of possible instrument settings to automatically determine the optimal set-up that allows the instrument to acquire data without Bit errors. PCIe Personalisation allows user to reduce set-up times and quickly start debugging their designs. The software automatically detects a TLA7SAxx module and brings up the PCI Express Protocol Analyser setup screen and starts an Auto-Configuration process. Once complete, users can begin acquiring data and viewing information in the Listing and Transaction windows that were automatically opened during the acquisition. Auto-Configuration configures the operating parameters of the Logic Protocol Analyser such as link speed, lane ordering and lane polarity based on the PCIe link characteristics. The setup window in combination with the calibration details table provide key indicators about the operating conditions of the system under test in near real time, viewable in a single, easy-to-use screen even before an acquisition is taken.
