Consider collision-avoidance systems that are beginning to appear in luxury cars that employ multiple cameras at strategic points around the vehicle to monitor the proximity of objects within a pre-defined range. Connecting these remote cameras to the centralised video processor that analyses each image in realtime poses a very real problem within the harsh automotive environment, especially when each camera may generate 16 or more bits of video information together with several control signals. Clearly, multiple parallel busses occupy considerable space and impose an undesirable weight burden; worse, this large amount of wiring can act as a very effective aerial to channel locally-generated high-impulse interference into the system's electronics.
The techniques required to enable automotive video applications highlight many of the challenges a design engineer faces in any system that combines multiple sources with a central display and/or control system. For instance, consider a representative in-vehicle system architecture that includes features such as a navigation aid and entertainment subsystems, cameras that scan lane-change manoeuvres and monitor an object's proximity to the vehicle's rear, and enhance night vision (figure 1).

Figure 1: Example of an in-vehicle system architecture.

As in an industrial application, a network such as CAN (controller-area-network) may transport supervisory and control information, while a sub-network moves video information. In European passenger vehicles especially, this sub-net may be the optical fibre based MOST (media-orientated systems transport) network that's gained limited acceptance for tasks such as streaming video from a remote DVD player to rear-seat screens.

LVDS support

Neither of these approaches suits moving video data directly from its source to a destination. One solution eliminating wide data busses employs LVDS (low voltage differential signalling), a high-speed physical layer interface. This current-loop technique uses an H-bridge output stage at the transmitter to steer approximately 3.5mA into one of two conductors that carry the signal to a receiver, with the relative direction of current flow determining the signal's polarity (figure 2).

Figure 2: Relying on LVDS (low voltage differential signalling).

A resistor of nominal 100 Ohms value at the receiver terminates the bus and imposes a differential voltage of around 350mV onto a common-mode voltage of 1.25V that's independent of the system's power supply voltage. These operating levels particularly suit 3.3V logic power supplies, but as the receiver has a common-mode voltage range of 50mV to 2.35V, an LVDS link will tolerate as much as a 1V ground shift between transmitter and receiver on supplies of 3V or less. This aids communication in distributed systems where a considerable DC shift can occur over the length of a car's wiring harness. The maximum short-circuit current is 24mA. The resistor value can lie from 90 to 132 Ohms to suit the characteristic impedance of the cabling, while the small voltage swing and the balanced nature of the current loop constrain EMI generation and reject common-mode noise. A failsafe feature ensures that receiver outputs default to logic ‘1' under fault conditions, such as loss of the transmission signal or short-circuiting the receiver's inputs. This feature makes it easy for system designers to detect hardware link errors.
Crucially, the current-mode logic and small signal swing allows very high speed operation with a theoretical maximum that approaches 2GHz assuming a lossless transmission medium. In practice, and depending on the interconnection system, the maximum transmission distance is around 10 metres. The standard leaves users free to choose interconnections such as PCB tracks, flexible PCBs, ribbon cables, twisted-pair cabling, and connectors to suit a point-to-point link (as figure 2 shows) or a multi-drop topology. As a result, LVDS applications range from backplanes in telecommunication racks to disk drive interfaces to interconnecting graphics processors to LCD screens in laptops.

SerDes simplifies

With a little modification, LVDS techniques can also perfectly suit transmitting video data over a short-hop serial link, such as within a vehicle. The key elements in this scheme are the transmitters and receivers that serialise and deserialise parallel video information into a format that suits serial links. Building on the company's expertise in dedicated serialiser/deserialiser (SerDes) devices for multi-GHz backplane links, Intersil has been sampling the first of a family of SerDes devices that simplify video links in automotive, consumer, and industrial use. Transmitting data in an LVDS-like format, the ISL34340 combines the serialiser/deserialiser functions to allow bidirectional operation over a single low cost differential pair, such as Twinax cable or a Cat5 Ethernet pair.
Comprising five major functional blocks, the ISL34340 has 27 parallel data inputs that accommodate 24-bit RGB component video in 8:8:8 format, together with its horizontal and vertical synchronization and data-enable signals (see figure 3).

Figure 3: Block diagram of the ISL343x0 video Serdes.

It uses a 64-pin thermally-enhanced TQFP. The otherwise identical ISL34320 shrinks the footprint into a 48-pin TQFP to suit reduced 16-bit video formats typical of camera systems. A single pin configures the chip as transmitter or receiver. The parallel video interface operates at normal CMOS levels, with each input capable of handling data rates from 6 to 45Mbit/s. A user-selectable dither generator is available to spread the noise spectrum across a wider bandwidth, constraining pixel-clock-related noise peaks. The core of the chip is the high-speed engine that's responsible for formatting and decoding the serial stream; unusually, its PLL (phase-locked loop) requires no external components. The core's major signal paths connect directly to the transceiver block, which uses transmitter pre-emphasis and receiver equalisation to maximise data rates over cable runs of up to 10 metres. To improve common-mode rejection, the transceiver allows AC coupling, which complements the 8B/10B encoding protocol to guarantee the DC balance that's essential to reliably recovering the embedded clock and data signals from the serial stream. Capable of data rates as high as 1.5Gbit/s, the transceiver is protected against ESD strikes and integrates the link's termination resistors. A BIST (built-in system test) block eases production and field test issues. A unique aspect of Intersil's ISL34320/340 devices is the implementation of a side channel feature. Apart from the video rate forward channel, the side channel deploys additional logic to allow control signals to be passed bi-directionally to and from the remote cable end. In typical operation, the system processor communicates with the ISL34320/340 via a standard I2C interface in slave mode, and can retrieve fault information such as cable disconnects. Uniquely, a TDM (time-division-multiplex) circuit allows the high-speed serial link to transport data between the I2C ports that would otherwise require a separate transport medium (figure 4).

Figure 4: A time-division-multiplex circuit allows the high-speed serial link to transport data between the I2C ports.

The video data transport block packages image data into the primary stream, while the separate side channel transport accepts data from the I2C port. This auxiliary channel can transmit set-up and control data via the serial link during one line of the video vertical retrace interval. By inserting sufficient turn-around time to ensure that the control data doesn't conflict with the video stream, a pair of chips can seamlessly exchange up to 224 bytes of data in each direction per video frame interval. This equates to 107kbit/s of raw data throughput at a 60Hz frame rate. Uses for the secondary transport mechanism include setting up a remote SerDes chip without the need for a separate long-haul I2C connection. In this scenario, the host processor can take advantage of the RAM area within the local (remote) SerDes device to assemble configuration data before triggering a transfer to the remote chip. It's also possible to perform register-to-register transfers between the SerDes pair, exchange data with an I2C EEPROM, or communicate with other I2C devices such as sensors. For example, by using an I2C-compatible device such as Intersil's ISL29000 ambient light sensor, the host can dynamically adjust the brightness of a remote LCD to balance the screen's contrast ratio and power consumption.

Typical applications

The ISL34320/340 devices are simple to apply and follow two general usage models (figure 5).

Figure 5: Two general usage models for the ISL34320/340 devices.

The top example shows the arrangement for driving a remote LCD from a central host processor. The host sets up the serialiser and deserialiser using the I2C interface and the SerDes chips' side transport channels. The host supplies the serialiser with digital component video data, synchronisation pulses, a data enable signal, and the pixel clock. The pixel clock is responsible for latching RGB data into the serialiser and also serves as the reference frequency that controls the serial transmission. The deserialiser reconstructs the video information using a local reference clock that's matched to the pixel clock's frequency. The lower example reverses the roles of the SerDes chips to enable a remote camera to stream video into the host system. In this case, the camera provides the pixel clock and a matching reference clock is necessary at the host end. In other respects, the circuit works as before. Intersil is sampling two automotive Serdes products today that are specified for operation from -40 to 105°C. The ISL34320 is a 6 to 37MHz 16 + 3-bits video Serdes in a 48-pin TQFP package. The ISL34340 6 to 45MHz, 24 + 3-bits video Serdes comes in 64-pin TQFP package. Both devices are currently undergoing full AECQ-100 qualification and production release is scheduled for Q1 2008.