CAD-tool productivity has been growing roughly linearly while gate counts, features and SoC complexity roughly doubles every two years. How can semiconductor manufacturers - often at the bottom of the manufacturing food chain - share the benefits and competitive advantages from this technology? With design cycles under extreme pressure, and OEMs forced to change specifications and features as new standards evolve, how can they ensure that they are not left out?

Increasingly, product-direction flexibility is heavily determined by the initial platform-based choices. Fundamentally, this enormous front-end investment makes business sense from a potential ROI perspective only if scalability, re-usability and portability can be exploited across multiple product generations. Consider the contrasts in sales and adoption cycles between fairly static, long existing products and new, digital consumer products such as those highlighted below. As the time from initial launch to perceived obsolescence shrinks, and products evolve from state-of-the-art to outdated in a matter of months, the planning, design and production tread mill runs faster. On top of this, there is the introduction of new features and standards in the audio, video, communications, and DRM community to consider.

Typical design flows may prove to be terrifying to the parties involved, both for their potentially unbounded open-endedness as well as the many possibilities of iterative re-entries. Consider the frequent challenge of fixing an inadequate timing-closure path: with the existence of a robust high-level model, repair may be greatly simplified. For example, suppose the critical-path analysis includes a rounding, and that a simple truncation might save two gate delays. Will the resulting change still meet some required standard, and will it also be undetectable if it is a part of a video or audio stream? Making these changes at a much higher level of abstraction means that the task of re-simulating and verifying can be sped up by a couple orders of magnitude, allowing changes at the RTL level to be re-synthesised more quickly.

Different TLMs (transaction-level models) allow rapid trade-offs between accuracy and simulation speeds. If cores are to be added, deleted, or exchanged, only those directly affected would have their high-level models altered within the total simulation. Software development could continue and precede the arrival of any new silicon. Verification suites - often including those required to meet industry and trade standards for audio or video streams, and their associated transport-delivery specifications - could be quickly re-run. There is a growing recognition of the importance of IP optimisation for the application. Some of the more sophisticated SoCs may have more than forty cores: With so much potential for rapid and simplified optimisation, it is only natural to anticipate that design teams would wish to integrate these different aspects together, integrating in such a way as to realise powerful synergies.

The CoWare-Sonics flow

Even as two totally isolated entities, Sonics SMX and CoWare's Platform Architect have seen frequent usage at the same customers, where common pressures of generating sophisticated SoCs with HMPs under tight schedules prevail. As efforts to simplify data flows between them proceeded, the following design-flow standard emerged. Again, video processing provides some unique challenges. When dealing with any perceptual codecs, audio or video, there are at present no generally accepted quantitative engineering metrics that correspond to subjective quality. Many speech, audio and video algorithms require certain bit-equivalence tests and artifact quantification thresholds to meet standards, but subjective analyses by a broad array of experts is still usually required. By raising the level of abstraction, video may be processed orders of magnitude faster, and design choices can be rapidly verified as acceptable or not. High-level models offer the ability to handle the burstiness of decompressed video data without unnecessary memory buses or extra pins: consider a typical backend video processor.

Using the smooth integration flow between Sonics StudioC and Platform Architect, different architecture settings can be simulated. The optimum architecture can be found by comparing the different analysis results. This methodology can be applied to optimise the different aspects of the architecture where, especially with video, the interconnect and memory subsystem need to be fine-tuned to reach the required specifications while minimising over-design.

With design cycles shrinking, time-to-market pressures increasing, and costs of delay skyrocketing, these challenges will not cease. As the available bandwidth is fixed, but the desire for more information grows, convergence will mean more pressure for more cores on more devices functioning at higher effective throughputs while using less power. However, the methodologies discussed and the enhancements motivated should continue to allow the phenomenal growth in features to continue into the foreseeable future, while still managing to shrink costs.