Can you describe briefly your main line of business?

Low power is the primary emerging competitive advantage for many, many chips today. Sequence is all about design-for -power (DFP), and encompasses an EDA tool flow from RTL to all the way through sign-off. Our mission is to help designers of complex semiconductor chips to achieve their design and implementation goals and meet time to market needs; to give them a competitive advantage. Sequence tools are used by designers in wireless, graphics, mobile-computing, networking and ASIC markets.

What is your best selling product and where do you ship it most? 

Sequence Design-for-Power (DFP) flow encompasses a complete solution from micro-architecture and RTL through gate-level implementation. A flagship product for us is Sequence PowerTheater. It is used by the design engineer, and offers three key advantages. The first one is early power analysis, at RTL, before it is too late to design proactively for power. Secondly, a portfolio of power reduction and power debug solutions is available at RTL, that has shown to reduce power from 25 to 50%. The third key benefit is awareness of the temporal component of power, the stimulus, including modal analysis and qualification of vectors for package selection and power grid design.

PowerTheater includes PowerTheater-65 for RTL analysis and reduction, and PowerTheater-Explorer, a cockpit and visualisation environment for power reduction.
We sell it strongly in North America, with about 30% in Europe and Asia.

What is your roadmap from there?

We are looking at additional products focusing on automated power reduction, from the RTL. As power management becomes main-stream, push-button power reduction is critical: for clocks, for datapath, for control logic, for memories, etc. Sequence is also always moving forward to support advanced power management techniques such as voltage / frequency scaling.

How do you differentiate from your competitors?

For front-end, RTL power estimation and management, Sequence has no peer. All Sequence tools fit seamlessly with all major vendor flows, including Cadence, Synopsys and Magma.

Any strategic move planned for the future?

Sequence will continue to create value for DFP through globalisation of customer support and R&D operations. We are also investing in a low power ecosystem through strategic partnerships with technology partners, EDA flow partners, IP partners, foundries, and design services companies. We see an increasing demand for low power design services, worldwide, so we are in the process of extending this area of our low power ecosystem.

What would make your life easier in this business?

From a technical viewpoint, Standards! Low power design is complex and challenging. The incidence of standards in low power will ease the task of the designer, and also of EDA companies in providing a smooth flow. We applaud the CPF and UPF low power standards; though we wish there will be a convergence of these two competing but very similar standards. From a business viewpoint, discounting practices in EDA continue to cripple the industry; and work against innovation that will ultimately benefit our customers in the design community. The EDA industry provides such high value and high levels of support, and is mission critical to the semiconductor business and its customers. A new business model, or at least practices that promote healthy EDA companies with healthy R&D investments, are called for.