While ensuring suitable input and output ratings is among the more obvious duties in designing a distributed power architecture, other attributes to take into account include transient performance, ripple and noise, EMC compatibility, and thermal design. The most basic design considerations for any converter are the input and output voltages and currents. The majority of POLs are offered with nominal input ranges of 3.3, 5, and 12V. Since 3.3 and 5V sources are typically well regulated, an input operating range of ±10% is adequate for such applications. Some product ranges, such as the LSN and LSM series, support a wider input-voltage range (for example 3.0 to 5.5V or 2.4 to 5.5V) to accommodate either nominal 3.3 or 5.0V inputs. Whereas these voltage rails tend to be well regulated, the source voltage for a 12V input may be governed by the performance of an IBC (intermediate bus converter). In the case of a quasi-regulated or so-called fixed-ratio converter, there is essentially no input-line regulation. When the range of permissible variations in a nominal 48VDC battery-back-up source - for example - are taken into account, the input operating range of the corresponding POL converter can be as wide as 9.6 to 14.1V.
Output ratings
The output voltages for POLs typically range from 0.8 to 5.0VDC. These tend to be buck regulators, having output voltage that are less than the input voltage. In addition, designers need to consider drop-out limitations when working with converters in the 3V input range. For a typical drop-out limit around 1.2V, a requirement for a 2.5V output could be satisfied from a 5 or 12V input, but not from 3.3V. Other options include fixed or variable output voltages, which allow designers to meet various system requirements. Some POL families, such as the LEN, and LQN series, offer a wide range of discrete output voltages that can also be trimmed within a range of ±10%, allowing designers to access just about any voltage between 0.75 and 5.0V. Other families can be trimmed over the full range of 0.75 to 5.0V. This can simplify the qualification process and material-management issues at the design phase by specifying a single part number that will fulfill multiple voltage requirements through the use of a single programming resistor for each point of use.
Modern POLs are typically classified in terms of output-current rating rather than output power, as current delivery tends to be the dominant limitation in practice. In most cases, this simply requires the selection of a model that carries an output-current rating that equals or exceeds that of the worst-case steady-state load. On the other hand, highly capacitive loads may require peak currents that significantly exceed the steady-state requirements. The effect of output-decoupling capacitors, for example, must be considered, as well as loads such as FPGAs that present a high capacitance due to large numbers of internal gates. In order to ensure monotonic rise of the output - to prevent spurious power-on resets - it is necessary to avoid current-limit inception, which will drive the output voltage down. In such cases, it will be necessary to examine the current-limit-inception point of the converter and/or mitigate the peak demand by implementing inrush-limiting circuitry.
Transient response
The transient response is an increasingly important performance parameter, especially for microprocessor and FPGA loads that are characterised by low core voltages, high current draw and fast load switching. Most POL datasheets describe the unit's transient performance according to proprietary criteria. This lack of a standardised set of test conditions precludes meaningful comparisons between POLs from different manufacturers. The magnitudes of load transients applied, as a percentage of the maximum rated output current, can vary from manufacturer to manufacturer, as can the starting and ending points of the load step. For example, a system may respond better to a 25 to 50% load step than to a 0 to 25% step.
In addition, some datasheets may specify only the positive load step and not the complementary negative sloping step. Applying a slower transient provides more opportunity for the converter and output capacitors to respond to the load change. Quoted slew rates can span more than three orders of magnitude, from as little as 0.5 to as much as 1200A/µs. Some datasheets do not even state the slew rate, which effectively prevents designers from assessing transient performance. The recovery time for the output voltage to return to within a percentage of the steady-state output voltage is also subject to variation.
Some datasheets specify 2%, while others may quote 1.5 or 1%. As a result, practical testing is usually necessary to confirm that the chosen POL will support the actual load transients. Note that designers can improve transient response by adjusting the output capacitance, provided that sufficiently low ESR is maintained. Adding input capacitance can also enhance response for longer and/or deeper transient steps. Adding converter phases also improves transient response by increasing the effective switching frequency and by allowing smaller output inductors and capacitors owing to the reduction in current per phase. As an example, the Murata JZY series of single-phase POLs allows up to four modules to be operated in parallel at 500kHz, 750kHz, or 1MHz, with the outputs interleaved to provide multiphase performance.
Ripple and noise
Output ripple and noise constitute unwanted deviations in the output voltage. These result naturally from the conversion process and are sometimes referred to as PARD (periodic and random deviations). For low DC voltages, the de facto industry standard for PARD is 1% for voltages greater than 5V or 50mVp-p for voltages below 5V. However, to reduce cost and size, some parts include less filtering and therefore may display maximum values above these figures. Most POL datasheets specify the amount of external decoupling capacitance - and attendant ESR - necessary to meet the published specifications. In virtually all cases, additional decoupling capacitance will mitigate output noise. To this end, it is useful to know the maximum output capacitance. Reflected ripple current describes the variation in input current resulting from converter switching. This fluctuation produces conducted EMI due to the ripple current itself, as well as radiated EMI from the input conductors. In addition, a ripple voltage is induced on the input rail as a consequence of the source impedance. Most Murata POLs incorporate internal input capacitors to reduce the reflected ripple current, but designers are also recommended to pay careful attention to board layout and use of input capacitance to maximise ripple-current mitigation. Ensuring a low ESR will reduce the ripple current, for example, although a large input capacitance with low ESR will result in increased inrush current to charge this capacitance as the input rail to the POL begins rising during start-up.
Between line and load regulation, most POLs are able to provide voltage regulation to within ±1% of the nominal output, which is better than what most applications require. A remote-sense feature can be important in maintaining regulation. At low output voltage and high output current, distribution drops produce a more profound effect on the output voltage at the load. While locating a POL regulator close to the point of load should address most of the distribution drop, remote-sense is able to address small remaining drops and account for system dynamics. The efficiency of the POL can have a significant effect on thermal management and design for units of relatively high efficiency. A difference in efficiency of 1 to 2% may not appear to offer significantly different performance in practice, but when comparing efficiencies of 94 and 96%, one POL will be dissipating 50% more heat than the other. As efficiencies approach 100%, the differences are magnified. To aid effective thermal design, Murata provides de-rating curves that plot the equilibrium between heat generated and evolved at various airflow rates and ambient air temperatures. When referring to this data, however, designers should also consider issues specific to the individual application, such as direction of airflow, obstructions, turbulence, eddy currents and dead-air zones.
Package selection
The maturing of distributed power design has precipitated several initiatives to standardise non-isolated converter footprints. Prime movers include industry coalitions such as POLA, DOSA, and the Z-One Alliance. Each has proposed a range of footprints that scale with output-current levels, which has made smaller SIP and SMT packages available to designers building DPAs. As far as package styles and materials are concerned, the modern trend towards open-frame construction delivers valuable cost savings. For applications that require more rugged packaging, five-sided steel cases with thermal encapsulant are the norm.
