Convergence is combining demanding technologies. In recent years, a broadband modem, a firewalled router, a wireless WiFi link and voice over IP (VoIP) telephony each represented a significant design achievement by itself. Today, all these functions are being combined into a single residential gateway. The processing burden is staggering. Consider HD DVD and Blu-ray Disc players that need to decode multi-channel HD video and audio streams, meanwhile running network connections, heavyweight operating systems and complex user navigation based on Java and/or XML/ECMAscript middleware.
Obsolescing the DSP
The performance curve of RISC architectures such as the 74K core is outpacing even advanced DSP architectures. Not only does the MIPS32 74K processor core clock faster than 1GHz today, but it also leverages multiple key new innovations including 27 critical new digital signal processing (DSP) instructions, a 26% speed-up via a dual-issue architecture and an out-of-order (OOO) execution capability that essentially allows the processor to rapidly decide the best option for instruction execution from several possible choices. Hardware enhancements were made to specifically enable C compilers to better generate optimal code, thus easing the burden on the software developer. Furthermore, DSP architectures require specialised programming skills that imply expensive engineer staffing and code maintenance. Most licensable DSP vendors have gone out of business and proprietary DSP designs are increasingly difficult to justify.
Instead, modest DSP turbocharging added to the MIPS32 24KE, 34K and 74K cores goes a long way to render the classical DSP obsolete. Attempting to perform real-time signal processing on cores traditionally used to run operating systems was once thought to be foolhardy. DSP-less real-time systems such as multi-channel VoIP have been proven to operate with carrier grade quality and are now commonplace. These cores incorporate three things that boost signal processing performance, especially within those deeply-nested, inner loops of code where each instruction cycle spared translates directly into exponentially faster overall throughput: A 32-bit, single-instruction/multiple-data (SIMD) subsystem that can process two 16-bit or four 8-bit operations in parallel; new instructions that efficiently handle common signal processing functions such as fractional fixed-point arithmetic, multiple rounding modes and bit-field operations to handle variable-length data compaction (Huffman coding, VLC) as well as bitstream packing and parsing; four 64-bit accumulator registers (instead of just one) that eliminates wasteful operations to read/write memory when the data should better be kept inside the CPU's register file.
Other innovations of the 74K core include the capability to pre-fetch multiple instructions and issue (execute) the address generations functions (AGEN) in parallel with arithmetic (ALU) operations. In the past, these two parallel operations had to be done sequentially. The core anticipates and reviews the execution and data dependencies contained in multiple upcoming instructions and rearranges the execution order to make better use of the clock cycles available, much like a chess player thinks ahead in the game to devise the best strategy to win. The 27 specific new DSP instructions can result in a 50% reduction of cycles spent in deeply-nested inner loops and enabling all relevant code to reside within the instruction cache, thereby eliminating expensive memory accesses. Improved orthogonality in the instruction set means that the C compiler can generate cleaner, more efficient code, can take better advantage of the SIMD architecture (auto-vectorisation) and can generate more compact code which reduces the thrashing of the instruction cache.
Multicore designs
Subsuming DSP functions onto the same MIPS core already present in the chip is an effective way to save silicon die area and eliminate royalty payments. Replacing the outgoing DSP core with an additional MIPS core dedicated to signal processing tasks is a good way to leverage the existing software code base and libraries already written and tested for MIPS across a multi-core design. It also enables instantaneous load balancing by moving code fragments from one processor core to another (without needing to port the code). It dramatically reduces software training, development and maintenance costs by reusing the existing software development and debugging tools for the MIPS core.
Demanding HD DVD and Blu-ray Disc audio specifications call for simultaneously performing two (primary, secondary) multi-channel audio decodes, sample rate conversion, re-mixing these multi-channel PCM streams and finally re-encoding the result using either DTS 1.5 Mbps or Dolby 640kbit/s encoding to pass the 5.1-channel sound across the S/PDIF connection (TOSlink, etc.) to legacy AVRs and power amplifiers. MIPS cores can handle this audio demand. Optimised and tested codec source code can be obtained directly from MIPS (Dolby, MPEG, SRS, etc.). This combined offering is compelling and makes perfect business sense.
Extremely area- and power-efficient implementations of video codecs are now possible using a dedicated hardware video engine to perform the "pixel" processing such as motion estimation/ compensation, transform coding and quantisation while the MIPS 74K core can focus on the "bitstream" processing such as packing/unpacking, Huffman coding, VLC, CAVLC and CABAC. In this way, each IP block performs the functions that it is best suited for, and together the result is a video processing solution that outperforms competing designs in price (number of gates), power (battery drain) and performance (able to handle real-time H.264 High Profile encoding or decoding). Furthermore, because the IP blocks can be programmed, the silicon licensed today becomes immortal even as standards change.
Getting started and getting done
No longer does a company need to hire and train specialists to write DSP software for specialised or proprietary DSP architectures. Instead, general purpose software development tools are used. Open source C compilers and debugging tools (GNU) and open source operating systems (Linux) are now widely used commercially. Microsoft Windows CE is another popular option. Because software already written for earlier MIPS cores also runs on the new 74K core, design reuse protects prior investments and saves time. In the digital consumer market where the MIPS architecture is widely used, embedded software is typically written first for MIPS or sometimes only for MIPS targets. This vast ecosystem lowers the barrier of entry for new or expanding companies that wish to participate in the burgeoning high-definition, digital living room business. Training and design services are widely available. Software for multimedia codecs, security, Java, networking and numerous popular wireless and wired connectivity standards is easily obtained and integrated.
To get a design done, hardware debugging and design verification is more complex than ever before. Fortunately, innovative technologies such as enhanced JTAG (EJTAG) and on-chip instrumentation IP such as PDTrace allows even the most complex multi-core and/or multi-threaded design to be effectively verified using real-time hardware probes connected to a simple PC.
