Designers increasingly require a comprehensive and easy-to-use development-tool suite that is optimised to identify and reduce power, maximise resource utilisation, and improve performance. With advanced layout processes and power-analysis capabilities, they can be even more efficient in the identification of the sources of power consumption in the design and the implementation of end solutions that consume the lowest possible power.

Power-driven layout

Designers of FPGAs have long relied on timing-driven layout to maximise performance. With little to no impact on timing performance, power-conscious users can now utilise a power-driven layout to reduce power consumption. Dynamic power savings can be quickly realised through the layout flow, which reduces the capacitive loading of the design nets based on estimated activities.

For example, the power consumed by nets in a typical Actel Igloo FPGA design is 40% or more of total dynamic power. However, after power-driven layout optimisation, the average power consumption of the FPGA can be reduced by 13%.

With today's power-driven layout capabilities, users can specify net-switching activities by using a VCD file, which can allow advanced users to fine-tune the tool's power optimiser for specific nets or scenarios. Other options for users include manually entering activities or simply allowing the tool to automatically estimate the net activities during layout. Automatic net-activity estimation affords users the convenience of power-driven layout without first having to perform a back-annotated simulation. On average, user-supplied VCD activities have been found to reduce the total power by an additional 2% on top of what was achievable using power-driven layout with automatic net-activity estimation alone.

Advanced power-analysis capabilities

Also critical to enabling power efficiency in portable designs is the ability to analyse the entire FPGA as well as specific portions of the device, such as nets, gates, I/Os, switching cycles, and spurious transitions, which individually contribute to overall power consumption in real-life-application functional modes. This functionality provides new avenues to identify major power "hot spots" in key parts of the design - users can then evaluate these and modify their design to reduce power.

Figure 1: Adressing power consumption.

Few designs, especially portable designs, are operated in active mode 100% of the time. Most portable applications operate in a combination of active, static, sleep or custom modes to conserve battery power. The ability to analyse functional modes - such as active, static or sleep, or custom modes (Figure 1) - is unique among FPGA tools. This means that users can create a report of a power profile based on the duration or percentage of operating time in each mode, which provides a more realistic report of power consumption in typical operation.

Figure 2: Smart power analysis.

Cycle-accurate power analysis allows designers to look at peak power per clock cycle as well as the average power for the entire simulation. Switching analysis, on the other hand, can identify hazards, or spurious transitions, that contribute to higher power consumption, allowing the user to address them and make corrections. According to some reports (Figure 2), hazards account for as much as 20% of total power consumed in a typical design.

Power-conscious design is becoming more critical. The combination of industry-leading low-power FPGAs with innovative power-optimising tools can enable significant power savings at both the chip and system level. With advanced layout optimisation and power-analysis capabilities, designers can be even more effective in the implementation of portable applications that consume the lowest possible power.