Many such low-power experts have recognised the need for a collective industry roadmap to improve low-power flows and are members of the 18-company Low-Power Coalition (LPC) under Silicon Integration Initiative (Si2). These leading companies - plus many more in the 24-company Power Forward Initiative - have already standardised on the Common Power Format (CPF), approved by the LPC as an Si2 standard early last year. This article will explore the design-methodology implications through one of many silicon success stories, courtesy of NXP Semiconductor.

 

Designing with multiple power domains

NXP's design challenge was a complex System on Chip, containing three voltage-scalable logic sections, three on-chip power domains, six off-chip power domains, and switchable pad-ring sections (Figure 1). Unlike previous clock-gating techniques, newer techniques, like voltage islands, are disruptive across the entire design methodology and thus required new solutions.

 

Figure 1: Power domains in NXP's complex SoC.

 

The design team's methodology included defining a complete hierarchical precedence mechanism to support IP reuse. Bottoms-up power-intent specifications were developed along with the RTL and needed to be reusable for multiple instantiations without colliding with the chip-level power specification. Top-down constraints drove consistent power intent to lower-level blocks that inherited common power-intent definitions. IP-block implementation required knowledge of external boundary-level power domains and state conditions. The NXP methodology used self-running test cases on the embedded CPU cores to drive a central power-mode controller, which in turn drove individual power-up and -down sequences across the chip. Rather than modify RTL to insert isolation cells, the design team used CPF as its golden power-intent specification, permitting a generic and scalable methodology from synthesis through routing.

 

CPF's virtual power domains

NXP found that the Virtual Power Domain feature in CPF permitted chip-level power domains to be visible during bottom-up IP-block implementation, easing chip assembly. The "analysis view" feature of CPF permitted the design team to manage the different constraints and libraries associated with each operating condition and power mode at a much higher level of abstraction. These features proved critical for complexity management, given there were so many additional power modes and transition states that greatly complicated timing optimisation and sign-off.
Such added complexity is particularly troublesome for backend implementation because of added checks to verify parameters such as proper isolation, power-logic connectivity and external interface behaviour (Figure 2). Layout is complicated by voltage islands and on-chip switches that limit floorplan alternatives and complicate power distribution. Level shifters require multiple voltage supplies and further complicate layout. Static timing sign-off is complicated with additional corner cases and modes due to logical paths spanning power domain boundaries.

 

Figure 2: External interface verification for power switching.

 

NXP's use of CPF yielded significant results. Power-aware simulations discovered that a time-out mechanism, critical to protecting against deadlock conditions on the communication bus, was itself being powered down in one particular mode. NXP engineers concluded that the use of CPF reduced back-end implementation time by a significant 50%, thus compensating for the 50% loss of productivity initially introduced by multi-supply-voltage design techniques. CPF features, such as virtual power domains and analysis views, became important for complexity management under the rigors of production design schedules. Following tape-out success, NXP concluded that CPF alleviated many of the expensive manual tasks in power management and has proven a solid foundation upon which to build.

 

Expanding the CPF

NXP, with many other LPC members, are currently adding enhanced features into CPF 1.1, expected to be ratified and published by mid-year. Important capabilities being added include enhancements to hierarchical IP reuse, memory (and other custom IP) modeling, power-network-component modeling, associating clocks to power-mode transitions, and support for power estimation. Besides defining a long-term low-power roadmap for the industry, the LPC has aligned on a complete power-aware reference flow from ESL through layout, has catalogued every known low-power design technique, and released a low-power glossary of terminology including practical definitions. Another active LPC working group is currently developing a data model and an application-programming interface to support rapid incremental "what-if" scenarios (Figure 3).

 

Figure 3: Top-level CPF data-model view.

 

Today, CPF 1.0 is in production reference flows at TSMC, UMC, Chartered, IBM, Samsung, SMIC, and STARC, while enjoying support from seven leading IP providers. 11 tool suppliers already use CPF, and over 50 tape-outs have been completed using CPF, including designs at Freescale, Fujitsu, NEC, and of course NXP. The LPC has released a free software CPF parser to ease practical and consistent integration of the standard, and recently hosted a well-received tutorial with 108 advance registrations and over 750 downloads within a 48-hour period. The good news is that you need not be a member to download the CPF 1.0 standard, CPF parser software, low-power glossary, CPF tutorial, or CPF pocket reference guide: all are openly available from the www.Si2.org web site. Whether you are an expert or a neophyte, I encourage you to take advantage of the public resources available from the LPC, and suggest you join us in developing improved low-power design-flow capabilities for the industry as a whole.