Silicon Laboratories has announced the expansion of its portfolio of reconfigurable, frequency-agile precision clocks to include a single input, single output jitter-attenuating clock multiplier IC. The new Si5319 Any-Rate Precision Clock is capable of generating any output frequency from either a crystal or reference clock input with 0.3 picoseconds jitter generation. The device supports a free-run mode of operation, enabling the device to be used as a frequency flexible, low jitter clock generator when supplied a crystal input. The Si5319 is suitable for providing clock synthesis, clock multiplication and jitter attenuation in high performance timing applications such as SONET/SDH/OTN line cards, WDM line cards, wireless basestations, synchronous Ethernet routers, test and measurement equipment and broadcast video.
The Si5319 is based on Silicon Labs' patented, third generation DSPLL technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated phase-locked loop (PLL) solution that eliminates the need for external voltage-controlled crystal oscillator (VCXO) and loop filter components. The Si5319 provides good frequency flexibility given its ability to accept any frequency from 2 kHz to 710 MHz and generate any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz.
The Si5319 provides a highly integrated, cost-effective jitter attenuation solution for next-generation multi-rate line cards that must support an array of client-side and line-side interfaces, including SONET/SDH, 1G/10G Ethernet, Fiber Channel, OTN and HD-SDI. A single Si5319 can generate all required reference frequencies with low jitter, eliminating the need for multiple high frequency VCXOs.
The Si5319 free-run mode of operation simplifies clock startup issues in high performance applications. In these systems, customers typically use a high frequency crystal oscillator (XO) to generate an initial reference clock for the transceiver driving the high speed fiber optic link. After initial startup, the system requires a reference clock that is synchronised to another clock in the system not available at startup. The Si5319 locks to a crystal input at startup and switches to an active input clock when available. No external mux components are required. The Si5319 is available now in a 6 x 6 mm, 36-lead QFN package. The device is available in three speed grades based on maximum output clock frequency.