During the past few years, Internet traffic has shown tremendous, rapid growth in fixed and mobile access markets. For mobile access, the recent increased demand for 3G smart phones and PDA-type devices will continue to drive the increase of mobile data traffic from the enterprise market side. On the general consumer side, the biggest driver for increased data traffic for the foreseeable future will be video downloads for watching and sharing. Resulting demands from users for faster access and shorter download times, while also seeking a richer media experience, will encourage service providers to add higher capacity 3.5G and 4G base stations to their existing wireless infrastructure.
In next generation base station architectures, increasing data rate capability and the push for a higher capacity of users per base station lead to increasing backplane speeds between radio and baseband cards. This overall bandwidth increase, in turn, trickles down to more multicore DSPs interconnected in a standard cluster configuration on the baseband card.
To meet system bandwidth increases while minimizing interconnect traces to limit board size, Serial RapidIO (sRIO) has emerged as the chosen standard protocol for baseband card architectures. As an open standard, sRIO combines low overhead packets for high-bandwidth efficiency with straightforward peer-to-peer support. This combination is ideal for supporting multiple DSPs in baseband applications.
Figure 1. Next-generation base station architecture
The central packet switch (CPS) is critical in quickly and correctly routing data packets for distribution among DSPs, processors, FPGAs, other switches, or any other sRIO-based devices (see Figure 1). The continuous increase in offerings of sRIO-enabled DSPs, ASSPs and FPGAs has equated to a healthy ecosystem for high performance, yet cost effective, modular solutions for next-generation base stations. Using a standard protocol, such as sRIO, gives base station architects and designers much flexibility.
For any given wireless infrastructure, matching growing user bandwidth demands by deploying the correct amount of system bandwidth capability in the field in a cost-effective manner is the big challenge for service providers. The most successful base station vendors will offer providers an easily scalable, modular, common platform base station architecture promoting reuse across multiple technologies in WCDMA, LTE, WiMAX and CDMA2000.
Scalability, modularity and reuse in base station architectures specifically equate to the need for a flexible sRIO interconnect solution for varying numbers of DSPs on the baseband cards and between multiple baseband cards. A typical baseband architecture has a single sRIO switch as the aggregation point between multiple DSPs and other elements, such as a control processor and, possibly, FPGAs. If multiple baseband cards exist, they may be connecting to another switch, possibly sRIO also. Present sRIO version 1.3 implementation supports per port 1x and 4x lane configurations at 1.25G, 2.5G and 3.125G lane rates. Depending on the system bandwidth and user capacity targets for any given base station architecture, combinations of 1x and 4x lane ports at different lane rates vary widely. The common usage of 1x to 4x lanes at 1.25G, 2.5G and 3.125G lane rates should eventually transition to 5G and 6.25G per lane speeds supported by sRIO version 2.0.
Figure 2. First-generation CPS
The first-generation CPS-16 and CPS-8 devices are optimised for DSP cluster applications at board level (see Figure 2). Their main function is to have a backplane interface that can connect to a backplane switch or directly to multiple RF cards.
The use of sRIO-enabled CPSs makes architecture reuse even easier. The CPS family of sRIO switches represents the widest range of port and link interconnect combinations available today to cover the entire range of applications from 4G and 3.5G to standard 3G architectures. The CPS family, combined with the Pre-Processing Switch (PPS) family, represents seven different sRIO pre-processing and enhanced switches, supporting multiple 1x and 4x lane configurations from 8 ports to 40 ports.
Figure 3. Second-generation CPS
The second-generation CPS 10Q and CPS 6Q are optimised for board-level DSP/ASIC cluster applications or module-level distributed processing application (see Figure 2). The physical lanes may be configured to work at 3.125, 2.5 or 1.25Gbits/s, and all lanes independently work in short haul or long haul.
The CPS family includes an array of unique features and capabilities that make it the best choice for sRIO interconnect solutions. In the CPS, as well as PPS families, enhanced SerDes quads are used to allow designers a high degree of flexibility in matching the correct number of 1x and 4x lanes to their application. Each enhanced quad can be implemented as one 4x port or 4 1x ports, supporting any two lane rates within a quad. Another useful feature is the packet trace function available on each port. Packet trace allows snooping of data streams at a user-defined target port, helpful for in-house and field diagnostics. An identified packet using the Trace function can be mirrored, filtered or eliminated per user requirements. For easy evaluation and development, the CPS family is offered with ATCA and microTCA hardware platforms, supported by several software development tools. The CPS and PPS families come with device access drivers, a graphical user interface (GUI), an application programming interface (API).
The rising use of PDA and smart phone mobile devices is quickly driving up mobile data traffic due to the higher percentage of multimedia Internet access. This continuous escalation of data traffic equates to required deployment of next-generation base stations that can meet the increased bandwidth needs. To do this, next-generation base stations require clusters of multicore DSPs connected via sRIO for higher baseband processing capability. The IDT CPS family provides the optimum switching solution to facilitate easy scalability in modular base station architectures.
