Driving the movement has been a growing recognition of the advantages serial flash memory offers in terms of lower pin-count, reduced board space, lower power and, ultimately, lower system cost. While standard parallel flash memories are available in 32-pin or larger PLCCs, serial flash memories using a standard 4-pin SPI interface come in compact 8-pin packages. Each additional pin, along with costs for signaling and associated power ground pin, drives up system costs. Controllers with higher pin counts require more board layers for signal routing, further increasing costs. Board space requirements climb as well, and pose a direct obstacle to designers' ongoing attempts to reduce end product footprint. Moreover, users' relentless demands for new features in products like handsets, portable media players (PMPs) and Bluetooth devices place today's designers in a bind. The more pins devoted to system memory, the fewer available to deliver the processing power and memory bandwidth needed to support new features.
Limited XiP support
Despite the many benefits serial flash memory offers, a challenge arises when a design calls for Execute-in-Place (XiP) capability. Typically, these programs are executed directly from parallel flash memory, which can be addressed as individual words, rather than copied to RAM to reduce total memory requirements. But serial flash memory's limited performance attributes have forced designers to couple SPI-based flash devices with shadow RAM, usually an SRAM, to support the fast access needed for XiP. While the use of shadow RAM accelerates code access, it also drives up system footprint and cost, and undermines the primary advantages of moving to serial flash. To address these bandwidth limitations, some flash memory developers have recently introduced new devices with 2-bit and 4-bit output. While these multi-bit approaches accelerate output into RAM, they fall well short of the performance required to support true XiP. Typically, these multi-bit devices boost performance by multiplexing the I/O, but they still rely on a number of artifacts of the original SPI architecture. For example, they use a cumbersome single-bit command structure that must switch back and forth between single-bit and multi-bit output schemes. Often these devices add extra commands for power management and look-ahead commands to reduce overhead. More often than not performance latencies are hidden in slower protocols. These multi-bit serial flash devices also rely on traditional SPI protection schemes that protect one-eighth, one-fourth or one-half of a memory array, but offer little flexibility beyond that. Finally, they offer little in the way of security, branching or write interrupt features.
Eliminating clock cycles
The question facing designers today is how to improve the performance of serial flash devices without sacrificing the technology's advantages in form factor or low power consumption? Recently, developers at Silicon Storage Technology (SST) devised a new architecture to deliver the performance advantages system designers working with parallel flash memories need, while retaining the low pin-count, low-power and low-cost advantages of serial flash. By doing so, this new architecture boosts serial flash performance to a level where designers can now use it to support true XiP applications without relying on code shadowing on an external SRAM.
The key was the development of a Serial Quad I/O (SQI) which uses a 4-bit multiplexed synchronous serial communications protocol to deliver performance better than comparable parallel flash memories. Manufactured in SST's proprietary CMOS SuperFlash process, these devices use a SPI-like serial command structure to support SPI protocols for Read, High-Speed Read and JEDEC ID Read. But this new architecture also combines code execution flexibility, fast write and erase, and low-power operation with improved code security. Operating at up to 80 MHz, the first family of products using this new technology, the SST 26 Series SQI devices, offer performance up to 320 Mbps sustained burst data rate. Devices operating at higher frequencies will be available soon.
Driving development was an effort to eliminate clock cycles. To offer true random access capability, the SQI family is built around a zero-latency nibble-wide architecture that, unlike traditional serial flash memories, allows read commands to start anywhere and continue beyond any physical internal boundary such as a page, block or plane without counting clocks. By using just two clocks for a command, two clocks for address and two clocks to turn the bus around, this approach offers single-Byte access at speeds roughly equivalent to the Byte-wide access available on existing parallel flash memories. By using dual-word or three-word code snippet access, designers can achieve random word access faster than comparable fast word-wide, 70 ns, parallel flash. For multi-word or multi-Byte access, the SQI architecture offers significantly faster performance than comparable fast Byte or word-wide parallel devices. To reduce access time, the new architecture supports 8-, 16-, 32- and 64-Byte burst mode operation with wrap around. This capability allows designers to execute code in burst snippets for RAM-less applications or fill cache line buffers for those applications where the system architecture uses pipelining to maximize bus bandwidth. The SQI architecture also allows the designer to use the memory in continuous burst mode for applications that require variable code sizes both with and without a cache line architecture.
Index jumping
One innovative way the new architecture reduces the number of clocks and accelerates data access is through read memory indexing. This capability allows the system to jump from one address to another within a 256-Byte page, within a 64-KByte block or from one block to another using indirect addressing. Because the system doesn't have to load an entire address, it can dramatically trim address overhead. In a page or block jump, for example, the user can reduce address overhead from six to four clocks. Jumps from block to block do not save clocks, but they help simplify code relocation and improve code portability.
By planning ahead, code developers can take advantage of this function to dramatically reduce the number of clocks needed for read accesses, and in the process, improve overall system performance. The memory array in the SQI architecture is divided into four 8-KByte and one 32-KByte top and four 8-KByte and one 32-KByte bottom (overlay) parameter blocks designed to store locations of code, user data or system information. The main array is arranged in 64-KByte (overlay) uniform blocks which are all further divided into small 4-KByte sectors to maximize erase flexibility.
One of the major deficiencies in current serial flash solutions is the absence of extensive memory protection capabilities. The SQI architecture addresses this need by offering individual software block locking in 16-, 32- or 64-KByte blocks. Each of the four 8-KByte top and bottom parameter blocks can be read or write locked to protect sensitive user or system information. In addition, the main array blocks can be configured in 32-KByte and 64-KByte blocks and write locked to avoid inadvertent writes to a sector.
A write protection lock-down feature prevents users from changing the protection scheme. In a separate area outside the memory array, the SQI architecture includes a one-time programmable secure ID area. This feature combines a unique 64-bit factory-programmed ID and a 128-bit user-programmable block. It can be used to set a random security code for applications such as a token for handshaking in HDMI public/private word keys. A security ID lockout command prevents any future writes to the security ID area. Fabricated in SST's SuperFlash CMOS process, the SQI devices offer 100,000 cycles endurance and better than 100 years data retention. Like all serial flash memories, power dissipation is low. Active read current is 15 mA typical at 80 MHz. Standby current is only 10 µA typical.
HallA5.138
