Spansion's MirrorBit ORNAND2 memory family is designed to support efficient read/write performance at a smaller die size. The initial single chip densities range from 1 to 4Gbit at both 1.8 and 3.0V using a Single Level Cell (SLC) architecture. The product uses MirrorBit charge-trapping technology and features a SONOS-like cell connected in a NAND array. The products with 3V operating voltage and an industrial temperature range are suitable for embedded applications. A managed NAND controller and interface functionalities are integrated with the memory on a single chip that offers simplified design. The handset platforms use a Store and Download architecture low-latency demand paging. This enables high-read performance of MirrorBit NOR and MirrorBit Eclipse products for code execution, and fast write performance of MirrorBit ORNAND2 products for data storage.
Hall A5.121
