Evatronix has upgraded its NAND Flash Controller IP core. Both Bose, Chaudhuri and Hocquenghem (BCH) algorithm and Open Core Protocol (OCP) socket enable the component's implementation in various SoC environments, as well as reduce the IP core's gate count. BCH algorithm introduces bit-level error correction for Multi Level Cell (MLC) memories and can handle random scattering of errors. OCP socket's isolation from bus specific decode/selection logic facilitates IP reuse by simplifying the core's connection to both renowned bus standards -- AMBA, Avalon, OPB, VCI -- and individual user's interfaces. The new controller supports MLC memories with 4Kbyte page size and up to 128Gbit of capacity. ONFi standard compliance offers operation of the controller with memories from diverse vendors, and a set of configurable features enable an application-tailored implementation.
